NXP Semiconductors Document Number: MPC5777M Rev. 6, 06/2016 Data Sheet: Technical Data MPC5777M 416 TEPBGA 512 TEPBGA MPC5777M Microcontroller 27mm x 27 mm 25 mm x 25 mm Data Sheet Three main CPUs, single issue, 32-bit CPU core complexes Dual phase-locked loops with stable clock domain for (e200z7), one of which is a dedicated lockstep core. peripherals and FM modulation domain for Power Architecture embedded specification computational shell compliance Dual crossbar switch architecture for concurrent access to Instruction set enhancement allowing variable length peripherals, flash, or RAM from multiple bus masters with encoding (VLE), encoding a mix of 16-bit and 32-bit end-to-end ECC instructions, for code size footprint reduction Hardware Security Module (HSM) to provide robust Single-precision floating point operations integrity checking of flash memory 16 KB Local instruction RAM and 64 KB local data System Integration Unit Lite (SIUL) RAM Boot Assist Module (BAM) supports factory programming 16 KB I-Cache and 4 KB D-Cache using serial bootload through UART Serial Boot Mode I/O Processor, dual issue, 32-bit CPU core complex Protocol. Physical interface (PHY) can be: (e200z4), with UART/LIN Power Architecture embedded specification compliance CAN Instruction set enhancement allowing variable length GTM104 generic timer module encoding (VLE), encoding a mix of 16-bit and 32-bit Enhanced analog-to-digital converter system with instructions, for code size footprint reduction Twelve separate 12-bit SAR analog converters Single-precision floating point operations Ten separate 16-bit Sigma-Delta analog converters Lightweight Signal Processing Auxiliary Processing Eight deserial serial peripheral interface (DSPI) modules Unit (LSP APU) instruction support for digital signal Two Peripheral Sensor Interface (PSI5) controllers processing (DSP) Three LIN and three UART communication interface 16 KB Local instruction RAM and 64 KB local data (LINFlexD) modules (6 total) RAM LINFlexD 0 is a Master/Slave 8 KB I-Cache LINFlexD 1, LINFlexD 2, LINFlexD 14, 8640 KB on-chip flash LINFlexD 15, and LINFlexD 16 are Masters Supports read during program and erase operations, and Four modular controller area network (MCAN) modules multiple blocks allowing EEPROM emulation and one time-triggered controller area network 404 KB on-chip general-purpose SRAM including 64 KB (M-TTCAN) standby RAM (+ 192 KB data RAM included in the External Bus Interface (EBI) CPUs). Of this 404 KB, 64 KB can be powered by a Dual routing of accesses to EBI separate supply so the contents of this portion can be Access path determined by access address preserved when the main MCU is powered down. Access path downstream of PFLASH controller Multichannel direct memory access controllers (eDMA): 2 Allows EBI accesses to share buffer and prefetch x 64 channels per eDMA (128 channels total) capabilities of internal flash Triple Interrupt controller (INTC) Allows internal flash accesses to be remapped to memories connected to EBI NXP reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.Table of Contents 1 Introduction 4 3.14.2 Power management integration 75 1.1 Document overview 4 3.14.3 3.3 V flash supply . 76 1.2 Description .4 3.14.4 Device voltage monitoring 77 1.3 Device feature .4 3.14.5 Power up/down sequencing . 79 1.4 Block diagram .7 3.15 Flash memory electrical characteristics 80 2 Package pinouts and signal descriptions 10 3.15.1 Flash memory program and erase 2.1 Package pinouts 11 specifications 80 2.2 Pin/ball descriptions .15 3.15.2 Flash memory FERS program and 2.2.1 Power supply and reference voltage pins/balls .15 erase specifications . 82 2.2.2 System pins/balls 16 3.15.3 Flash memory Array Integrity and Margin 2.2.3 LVDS pins/balls .17 Read specifications . 83 3 Electrical characteristics .21 3.15.4 Flash memory module life specifications . 84 3.1 Introduction 21 3.15.5 Data retention vs program/erase cycles 84 3.2 Absolute maximum ratings 21 3.15.6 Flash memory AC timing specifications 85 3.3 Electrostatic discharge (ESD) 23 3.15.7 Flash read wait state and address pipeline 3.4 Operating conditions .23 control settings . 85 3.5 DC electrical specifications 27 3.16 AC specifications . 86 3.6 I/O pad specification .30 3.16.1 Debug and calibration interface timing . 86 3.6.1 I/O input DC characteristics 31 3.16.2 DSPI timing with CMOS and LVDS pads . 94 3.6.2 I/O output DC characteristics .35 3.16.3 FEC timing . 110 3.7 I/O pad current specification .42 3.16.4 FlexRay timing 115 3.8 Reset pad (PORST, ESR0) electrical characteristics 45 3.16.5 PSI5 timing . 118 3.9 Oscillator and FMPLL 48 3.16.6 UART timing 118 3.10 ADC specifications 53 3.16.7 External Bus Interface (EBI) Timing 119 3.10.1 ADC input description 53 3.16.8 I2C timing . 122 3.10.2 SAR ADC electrical specification 54 3.16.9 GPIO delay timing . 124 3.10.3 S/D ADC electrical specification 58 3.16.10Package characteristics . 124 3.11 Temperature sensor .67 3.17 416 TEPBGA (production) case drawing . 125 3.12 LVDS Fast Asynchronous Serial Transmission 3.18 416 TEPBGA (emulation) case drawing 127 (LFAST) pad electrical characteristics .67 3.19 512 TEPBGA case drawing . 130 3.12.1 LFAST interface timing diagrams .68 3.20 Thermal characteristics . 132 3.12.2 LFAST and MSC/DSPI LVDS interface 3.20.1 General notes for specifications at electrical characteristics 69 maximum junction temperature . 132 3.12.3 LFAST PLL electrical characteristics .72 4 Ordering information 134 3.13 Aurora LVDS electrical characteristics .73 5 Document revision history 137 3.14 Power management: PMC, POR/LVD, sequencing .75 3.14.1 Power management electrical characteristics 75 MPC5777M Microcontroller Data Sheet, Rev. 6 2 NXP Semiconductors