Freescale Semiconductor
Document Number: MSC8157E
Rev. 2, 12/2013
Data Sheet
MSC8157E
FC-PBGA783
29 mm 29 mm
Six-Core Digital Signal
Processor with Security
Six StarCore SC3850 DSP subsystems, each with an SC3850 DSP High-speed serial interface with a 10-lane SerDes PHY that
core, 32 Kbyte L1 instruction cache, 32 Kbyte L1 data cache, supports two Serial RapidIO interfaces, one PCI Express
unified 512 Kbyte L2 cache configurable as M2 memory in interface, six CPRI lanes, and two SGMII interfaces
64 Kbyte increments, memory management unit (MMU), (multiplexed). The Serial RapidIO interfaces support x1/x2/x4
extended programmable interrupt controller (EPIC), two operation up to 5 Gbaud with an enhanced messaging unit
general-purpose 32-bit timers, debug and profiling support, (eMSG) and two DMA units. The PCI Express controller supports
low-power Wait, Stop, and power-down processing modes, and 32- and 64-bit addressing, x1/x2/x4 link. The six CPRI controllers
ECC/EDC support. can support six lanes up to 6.144 Gbaud.
Chip-level arbitration and switching system (CLASS) that QUICC Engine technology subsystem with dual RISC
provides full fabric non-blocking arbitration between the cores processors, 48 Kbyte multi-master RAM, 48 Kbyte instruction
and other initiators and the M2 memory, shared M3 memory, RAM, supporting two communication controllers for two Gigabit
DDR SRAM controller, device configuration control and status Ethernet interfaces (RGMII or SGMII), to offload scheduling
registers, MAPLE-B, and other targets. tasks from the DSP cores, and an SPI.
3072 Kbyte 128-bit wide M3 memory, 2048 Kbytes of which can I/O Interrupt Concentrator consolidates all chip maskable
be turned off to save power. interrupt and non-maskable interrupt sources and routes then to
96 Kbyte boot ROM. INT_OUT/CP_TX_INT, NMI_OUT/CP_RX_INT, and the cores.
Three input clocks (one global and two differential). UART that permits full-duplex operation with a bit rate of up to
Six PLLs (three global, two Serial RapidIO, one DDR PLLs). 6.25 Mbps.
Second generation Multi-Accelerator Platform Engine for Two general-purpose 32-bit timers for RTOS support per SC3850
Baseband (MAPLE-B2) with a second generation programmable core, four timer modules with four 16-bit fully programmable
system interface (PSIF2); Turbo encoding and decoding; Viterbi timers, two timer modules with four 32-bit fully programmable
decoding; FFT/iFFT and DFT/iDFT processing; downlink chip timers; and eight software watchdog timers (SWT).
rate processing; CRC processing and insertion; equalization Eight programmable hardware semaphores.
processing and matrix inversion; uplink batch and fast processing. Up to 32 virtual interrupts and a virtual NMI asserted by simple
Some MAPLE-B2 processors can be disabled when not required write access.
2
to reduce overall power consumption. I C interface.
Security Engine (SEC) optimized to process all the algorithms Up to 32 GPIO ports, sixteen of which can be configured as
associated with IPSec, IKE, SSL/TLS, 3GPP, and LTE using 4 external interrupts.
crypto-channels with multi-command descriptor chains, Boot interface options include Ethernet, Serial RapidIO interface,
2
integrated controller for assignment of the eight execution units I C, and SPI.
(PKEU, DEU, AESU, AFEU, MDEU, KEU, SNOW, and the Supports IEEE Std. 1149.6 JTAG interface
random number generator (RNG), and XOR engine to accelerate Low power CMOS design, with low-power standby and
parity checking for RAID storage applications. power-down modes, and optimized power-management circuitry.
One DDR controllers with up to a 667 MHz clock (1333 MHz 45 nm SOI CMOS technology.
data rate), 64/32 bit data bus, supporting up to a total 2 Gbyte in
up to four banks (two per controller) and support for DDR3.
DMA controller with 32 unidirectional channels supporting 16
memory-to-memory channels with up to 1024 buffer descriptors
per channel, and programmable priority, buffer, and multiplexing
configuration. It is optimized for DDR SDRAM.
20112013 Freescale Semiconductor, Inc.
DMA 32 ch
SEC
Table of Contents
1 Pin Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Figure 11.DDR SDRAM Output Timing . . . . . . . . . . . . . . . . . . . . . 57
1.1 FC-PBGA Ball Layout Diagram. . . . . . . . . . . . . . . . . . . .3 Figure 12.DDR3 Controller Bus AC Test Load. . . . . . . . . . . . . . . . 57
1.2 Signal Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Figure 13.DDR3 SDRAM Differential Timing Specifications . . . . . 57
2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Figure 14.Differential Measurement Points for Rise and Fall Time 59
2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Figure 15.Single-Ended Measurement Points for Rise and Fall Time
2.2 Recommended Operating Conditions. . . . . . . . . . . . . .40 Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .41 Figure 16.Test Measurement Load . . . . . . . . . . . . . . . . . . . . . . . . 61
2.4 CLKIN/MCLKIN Requirements . . . . . . . . . . . . . . . . . . .41 Figure 17.Single Frequency Sinusoidal Jitter Limits for Data Rates for
2.5 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .41 3.125 Gbps and Below . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.6 AC Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . .54 Figure 18.Single Frequency Sinusoidal Jitter Limits for Data Rate 5.0
3 Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . .73 Gbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Figure 19.SGMII AC Test/Measurement Load. . . . . . . . . . . . . . . . 66
5 Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 Figure 20.Single Frequency Sinusoidal Jitter Limits for Baud Rate
6 Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 <3.125 Gbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 21.Single Frequency Sinusoidal Jitter Limits for Baud Rate
3.125 Gbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
List of Figures
Figure 22.Timer AC Test Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 1. MSC8157E Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 23.MII Management Interface Timing. . . . . . . . . . . . . . . . . 68
Figure 2. MSC8157E FC-PBGA Package, Top View . . . . . . . . . . . 3
Figure 24.RGMII AC Timing and Multiplexing . . . . . . . . . . . . . . . . 69
Figure 3. Differential Voltage Definitions for Transmitter/Receiver 43
Figure 25.SPI AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 4. Receiver of SerDes Reference Clocks . . . . . . . . . . . . . 44
Figure 26.SPI AC Timing in Slave Mode (External Clock). . . . . . . 70
Figure 5. SerDes Transmitter and Receiver Reference Circuits. . 45
Figure 27.SPI AC Timing in Master Mode (Internal Clock) . . . . . . 71
Figure 6. Differential Reference Clock Input DC Requirements
Figure 28.Test Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . 72
(External DC-Coupled) . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 29.Boundary Scan (JTAG) Timing . . . . . . . . . . . . . . . . . . . 72
Figure 7. Differential Reference Clock Input DC Requirements
Figure 30.Test Access Port Timing . . . . . . . . . . . . . . . . . . . . . . . . 73
(External AC-Coupled) . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 31.TRST Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 8. Single-Ended Reference Clock Input DC Requirements 47
Figure 32.MSC8157E Mechanical Information, 783-ball FC-PBGA
Figure 9. DDR3 SDRAM Interface Input Timing Diagram . . . . . . 55
Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 10.MCK to MDQS Timing . . . . . . . . . . . . . . . . . . . . . . . . . 56
DDR Interface 64/32-bit
1333 MHz data rate
I/O-Interrupt
JTAG IEEE 1149.6
Concentrator
DDR M3 Memory
Controller 3072 Kbyte
UART
Clocks
Timers
CLASS
Reset
Semaphores
SC3850 CLASS1
Virtual
DSP Core QUICC
Interrupts
High-Speed
CPRI data WR
Engine
32 Kbyte 32 Kbyte
Serial MAPLE-B2
Two SGMII Boot ROM
Subsystem
L1 L1
Interface
ICache DCache
2
I C
512 Kbyte
L2 Cache / M2 Memory
Other
Modules
Six DSP Cores at 1 GHz
Two Serial RapidIO x1/x2/x4 up to 5 Gbaud
Two RGMII Six lanes CPRI v4.1 up to 6.144 Gbaud
SPI PCI-Express x1/x2/x4 up to 5 Gbaud
Two SGMII
Note: The arrow direction indicates master or slave.
Figure 1. MSC8157E Block Diagram
MSC8157E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 2
2 Freescale Semiconductor