N74F08D,623 NXP

INTEGRATED CIRCUITS 74F08 Quad two-input AND gate Product specification 1995 Apr 19 IC15 Data Handbook Philips SemiconductorsPhilips Semiconductors Product specification Quad 2-input AND gate 74F08 PIN CONFIGURATION 74F08 Available for industrial range (40C to +85C) D0a 1 14 V CC TYPE TYPICAL TYPICAL D0b 2 13 D3b PROPAGATION SUPPLY CURRENT Q0 3 12 D3a DELAY (TOTAL) D1a 4 11 Q3 74F08 4.1ns 7.1mA D1b 5 10 D2b Q1 6 9 D2a GND 7 8 Q2 SF00038 ORDERING INFORMATION COMMERCIAL RANGE INDUSTRIAL RANGE DESCRIPTION PKG DWG # V = 5.0V 10%, T = 0C to +70C V = 5.0V 10%, T = 40C to +85C CC amb CC amb 14-pin plastic DIP N74F08N I74F08N SOT27-1 14-pin plastic SO N74F08D I74F08D SOT108-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW Dna, Dnb Data inputs 1.0/1.0 20A/0.6mA Qn Data output 50/33 1.0mA/20mA NOTE: One (1.0) FAST unit load is defined as: 20A in the High state and 0.6mA in the Low state. LOGIC DIAGRAM FUNCTION TABLE 1 INPUTS OUTPUT D0a 3 2 Q0 D0b Dna Dnb Qn 4 D1a 6 L L L 5 Q1 D1b L H L 9 D2a 8 Q2 H L L 10 D2b H H H 12 11 V = Pin 14 CC D3a Q3 13 GND = Pin 7 NOTES: D3b H = High voltage level SF00052 L = Low voltage level LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) 12 4 5 9 101213 & 1 3 2 D0a D0bD1a D1bD2a D2b D3a D3b 4 6 5 Q0 Q1 Q2 Q3 9 8 10 V = Pin 14 CC 36 8 11 GND = Pin 7 12 SF00040 11 13 SF00053 2 1995 Apr 19 8530328 15145