N74F126D,602 NXP

74F126 Quad buffers 3-State Rev. 4 23 January 2013 Product data sheet 1. General description The 74F126 provides four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A LOW at nOE causes the outputs to assume a high-impedance OFF-state. 2. Features and benefits High impedance NPN base inputs for reduced loading (20 A in HIGH and LOW states) 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version N74F126N 0 C to +70C DIP14 plastic dual in-line package 14 leads (300 mil) SOT27-1 N74F126D 0 C to +70 C SO14 plastic small outline package 14 leads body width SOT108-1 3.9 mm74F126 NXP Semiconductors Quad buffers 3-state 4. Functional diagram 2 1A 1Y 3 2 1 3 1OE 1 1 EN1 5 2A 2Y 6 5 6 4 2OE 4 3A 3Y 8 9 9 8 10 3OE 10 12 4A 4Y 11 12 11 4OE 13 13 mna235 mna236 Fig 1. Logic symbol Fig 2. IEC logic symbol 5. Pinning information 5.1 Pinning Fig 3. Pin configuration DIP14 and SO14 package 5.2 Pin description Table 2. Pin description 1 Symbol Pin Description Unit load Load value HIGH/LOW HIGH/LOW 1OE to 4OE 1, 4, 10, 13 output enable input (active HIGH) 1.0/0.033 20 A/20 A 1A to 4A 2, 5, 9, 12 data input 1.0/0.033 20 A/20 A 1Y to 4Y 3, 6, 8, 11 data output 750/106.7 15 mA/64 mA GND 7 ground (0 V) - - V 14 supply voltage - - CC 74F126 All information provided in this document is subject to legal disclaimers. NXP B.V. 2013. All rights reserved. Product data sheet Rev. 4 23 January 2013 2 of 12