INTEGRATED CIRCUITS
74F194
4-bit bidirectional universal shift register
Product specification 1989 Apr 04
IC15 Data Handbook
Philips Semiconductors Product specification
4-bit bidirectional universal shift register 74F194
FEATURES PIN CONFIGURATION
Shift right and shift left capability
MR 1 16
V
CC
Synchronous parallel and serial data transfer
D 2 15 Q0
SR
Easily expanded for both serial and parallel operation
D0 3 14 Q1
Asynchronous Master Reset
D1 4 13 Q2
D2 5 12 Q3
Hold (do nothing) mode
D3 6 11 CP
DESCRIPTION
D 7 10 S1
SL
The functional characteristics of the 74F194 4-Bit Bidirectional Shift
GND 8 9 S0
Register are indicated in the Logic Diagram and Function Table. The
register is fully synchronous, with all operations taking place in less
SF00167
than 9ns (typical) for 74F, making the device especially useful for
implementing very high speed CPUs, or for memory buffer registers.
The 74F194 design has special logic features which increase the
TYPICAL
range of application. The synchronous operation of the device is
TYPE TYPICAL f SUPPLY CURRENT
MAX
determined by two Mode Select inputs, S0 and S1. As shown in the (TOTAL)
Mode Select-Function Table, data can be entered and shifted from
74F194 150MHz 33mA
left to right (shift right, Q0Q1, etc.), or right to left (shift left,
Q3Q2, etc.), or parallel data can be entered, loading all 4 bits of
the register simultaneously. When both S0 and S1 are Low, existing
ORDERING INFORMATION
data is retained in a hold (do nothing) mode. The first and last
COMMERCIAL RANGE
stages provide D-type Serial Data inputs (D , D ) to allow
SR SL
DESCRIPTION V = 5V 10%, PKG DWG #
CC
multistage shift right or shift left data transfers without interfering
T = 0C to +70C
amb
with parallel load operation. Mode Select and data inputs on the
16-pin plastic DIP N74F194N SOT38-4
74F194 are edge-triggered, responding only to the Low-to-High
transition of the Clock (CP). Therefore, the only timing restriction is
16-pin plastic SO N74F194D SOT109-1
that the Mode Select and selected data inputs must be stable one
setup time prior to the Low-to-High transition of the clock pulse.
Signals on the Mode Select, Parallel Data (D0D3) and Serial Data
(D , D ) can change when the clock is in either state, provided
SR SL
only the recommended setup and hold times, with respect to the
clock rising edge, are observed. The four Parallel Data inputs
(D0D3) are D-type inputs. Data appearing on (D0D3) inputs when
S0 and S1 are High is transferred to the Q0Q3 outputs
respectively, following the next Low-to-High transition of the clock.
When Low, the asynchronous Master Reset (MR) overrides all other
input conditions and forces the Q outputs Low.
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW
D0D3 Parallel data inputs 1.0/1.0 20A/0.6mA
D Serial data input (Shift Right) 1.0/1.0 20A/0.6mA
SR
D Serial data input (Shift Left) 1.0/1.0 20A/0.6mA
SL
S0, S1 Mode Select inputs 1.0/1.0 20A/0.6mA
CP Clock Pulse input (active rising edge) 1.0/1.0 20A/0.6mA
MR Asynchronous master Reset input (Active Low) 1.0/1.0 20A/0.6mA
Q0Q3 Data outputs 50/33 1.0mA/20mA
NOTE: One (1.0) FAST unit load is defined as: 20A in the High state and 0.6mA in the Low state.
2
April 4, 1989 8530354 96224