NPIC6C596D-Q100 NXP

NPIC6C596-Q100 Power logic 8-bit shift register open-drain outputs Rev. 2 4 July 2013 Product data sheet 1. General description The NPIC6C596-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and open-drain outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR resets both the shift register and storage register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register is always one clock pulse ahead of the storage register. To provide additional hold time in cascaded applications, the serial output QS7 is clocked out on the falling edge of SHCP. Data in the storage register drives the gate of the output extended-drain NMOS (EDNMOS) transistor whenever the output enable input (OE) is LOW. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the registers. The open-drain outputs are 33 V/100 mA continuous current extended-drain NMOS transistors designed for use in systems that require moderate load power such as LEDs. Integrated voltage clamps in the outputs provide protection against inductive transients making the device suitable for power driver applications such as relays, solenoids and other low-current or medium-voltage loads. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from 40 C to +125 C Low R DSon Eight Power EDNMOS transistor outputs of 100 mA continuous current 250 mA current limit capability Output clamping voltage 33 V 30 mJ avalanche energy capability Enhanced cascading for multiple stages All registers cleared with single input Low power consumption ESD protection: HBM AEC-Q100-002 revision D exceeds 2500 V CDM AEC-Q100-011 revision B exceeds 1000 VNexperia NPIC6C596-Q100 Power logic 8-bit shift register open-drain outputs 3. Applications LED sign Graphic status panel Fault status indicator 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version NPIC6C596D-Q100 40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm NPIC6C596PW-Q100 40 C to +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mm NPIC6C596BQ-Q100 40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced SOT763-1 very thin quad flat package no leads 16 terminals body 2.5 3.5 0.85 mm 5. Functional diagram 2 DS 15 10 SHCP STCP 15 SHCP Q7S 9 3 8-STAGE SHIFT REGISTER Q0 7 4 MR Q1 5 Q2 2 6 DS Q3 10 11 STCP 8-BIT STORAGE REGISTER Q4 12 Q5 13 Q6 14 8 OE Q7 OPEN-DRAIN OUTPUTS 9 Q7S Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 MR OE 78 3 4 5 6 11 12 13 14 aaa-002547 aaa-002548 Fig 1. Logic symbol Fig 2. Functional diagram NPIC6C596 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 2 4 July 2013 2 of 21