INTEGRATED CIRCUITS 74F244/74F244B Octal buffers (3-State) Product specification 1994 Dec 05 IC15 Data Handbook Philips SemiconductorsPhilips Semiconductors Product specification Octal buffers (3-State) 74F244/74F244B FEATURES DESCRIPTION The 74F244 is an octal buffer that is ideal for driving bus lines of Octal bus interface buffer memory address registers. The outputs are all capable of 3-State output buffer sink 64mA sinking 64mA and sourcing up to 15mA, producing very good capacitive drive characteristics. The device features two output 15mA source current enables, OEa and OEb, each controlling four of the 3-State outputs. Guaranteed output skew less than 2.0ns (74F244B) The 74F244B is functionally equivalent to the 74F244. It has been designed to reduce effects of ground noise. Other advantages are Reduced ground bounce (74F244B) noted in the features. Reduced I (74F244B) CC Reduced loading (74F244B I = 40A) IL TYPICAL TYPICAL SUPPLY TYPE PROPAGATION Split lead frame offers increased noise immunity (74F244B) CURRENT (TOTAL) DELAY Industrial temperature range available (-40C to +85C) for 74F244 4.0ns 53mA 74F244 74F244B 4.0ns 33mA 74F244 available in SSOP Type II package ORDERING INFORMATION ORDER CODE COMMERCIAL RANGE INDUSTRIAL RANGE PKGPKG DWGDWG DESCRIPTION V = 5V 10%, V = 5V 10%, CC CC T = 0C to +70C T = -40C to +85C amb amb 20-pin plastic DIP N74F244N, N74F244BN I74F244N SOT146-1 20-pin plastic SOL N74F244D, N74F244BD I74F244D SOT163-1 20-pin plastic SSOP II N74F244DB SOT339-1 INPUT AND OUTPUT LOADING AND FAN OUT TABLE 74F (U.L.) LOAD VALUE PINS DESCRIPTION HIGH/LOW HIGH/LOW Ian, Ibn Data inputs (74F244) 1.0/2.67 20A/1.6mA Data inputs (74F244B) 1.0/0.067 20A/40A OEa, OEb Output enable inputs (active low) (74F244) 1.0/1.67 20A/1.0mA Output enable inputs (active low) (74F244B) 1.0/0.067 20A/40A Yan, Ybn Data outputs 750/106.7 15mA/64mA NOTE: One (1.0) FAST unit load is defined as: 20A in the high state and 0.6mA in the low state. PIN CONFIGURATION LOGIC SYMBOL 1 20 OEa V CC 2 4 6 8 17 15 13 11 2 19 Ia0 OEb 3 18 Yb0 Ya0 Ia0 Ia1 Ia2 Ia3 Ib0 Ib1 Ib2 Ib3 4 17 Ia1 Ib0 5 16 Yb1 Ya1 1 OEa 19 OEb 6 15 Ia2 Ib1 7 14 Yb2 Ya2 Ya0 Ya1 Ya2 Ya3 Yb0 Yb1 Yb2 Yb3 Ia3 8 13 Ib2 Yb3 9 12 Ya3 18 16 14 12 3 5 7 9 GND 10 11 Ib3 V = Pin 20 CC GND = Pin 10 SF00228 SF00227 2 1994 Dec 5 853-0357 14381