Document Number: P4080EC Freescale Semiconductor Rev. 4, 04/2013 Data Sheet: Technical Data P4080/P4081 QorIQ Integrated Processor FC-PBGA1295 37.5 mm x 37.5 mm Hardware Specifications The P4080/P4081 QorIQ integrated communication Two serial RapidIO 1.2 controllers/ports processor combines eight Power Architecture processor Enhanced secure digital host controller (SD/MMC) cores with high-performance data path acceleration logic and Enhanced serial peripheral interfaces (eSPI) network and peripheral bus interfaces required for High-speed USB controller (USB 2.0) networking, telecom/datacom, wireless infrastructure, and Host and device support mil/aerospace applications. Enhanced host controller interface (EHCI) ULPI interface to PHY This chip can be used for combined control, data path, and Data Path Acceleration Architecture (DPAA) incorporating application layer processing in routers, switches, base station acceleration for the following functions: controllers, and general-purpose embedded computing. Its Frame manager (FMan) for packet parsing, high level of integration offers significant performance classification, and distribution benefits compared to multiple discrete devices, while also Queue manager (QMan) for scheduling, packet greatly simplifying board design. sequencing, and congestion management This chip includes the following function and features: Hardware buffer manager (BMan) for buffer allocation and de-allocation Eight e500-mc Power Architecture cores, each with a Encryption/decryption (SEC 4.0) backside 128 KB L2 cache with ECC Regex pattern matching (PME 2.0) Three levels of instructions: user, supervisor, and 1295 FC-PBGA package hypervisor Independent boot and reset Secure boot capability CoreNet fabric supporting coherent and non-coherent transactions amongst CoreNet end-points A frontside 2 MB L3 Cache with ECC CoreNet bridges between the CoreNet fabric the I/Os, data path accelerators, and high and low speed peripheral interfaces Two 10-Gigabit Ethernet (XAUI) controllers One 10-Gigabit Ethernet (XAUI) controller on P4081 Eight 1-Gigabit Ethernet controllers Two 64-bit DDR2/DDR3 SDRAM memory controllers with ECC Multicore programmable interrupt controller (MPIC) 2 Four I C controllers Four 2-pin UARTs or two 4-pin UARTs Two 4-channel DMA engines Enhanced local bus controller (eLBC) Three PCI Express 2.0 controllers/ports 2011-2013 Freescale Semiconductor, Inc. All rights reserved.Table of Contents 1 Pin Assignments and Reset States .3 2.20 High-Speed Serial Interfaces (HSSI) . 101 1.1 1295 FC-PBGA Ball Layout Diagrams 3 3 Hardware Design Considerations 129 1.2 Pinout List 9 3.1 System Clocking 129 2 Electrical Characteristics 52 3.2 Supply Power Setting 137 2.1 Overall DC Electrical Characteristics 52 3.3 Power Supply Design 139 2.2 Power Sequencing 57 3.4 Decoupling Recommendations . 140 2.3 Power Down Requirements 59 3.5 SerDes Block Power Supply Decoupling 2.4 Power Characteristics 59 Recommendations . 140 2.5 Thermal .62 3.6 Connection Recommendations . 141 2.6 Input Clocks .63 3.7 Recommended Thermal Model . 149 2.7 RESET Initialization .65 3.8 Thermal Management Information 149 2.8 Power-on Ramp Rate 66 4 Package Information 151 2.9 DDR2 and DDR3 SDRAM Controller 66 4.1 Package Parameters for the 2.10 eSPI .74 P4080/P4081 FC-PBGA 151 2.11 DUART .76 4.2 Mechanical Dimensions of the 2.12 Ethernet: Data Path Three-Speed Ethernet (dTSEC), P4080/P4081 FC-PBGA 152 Management Interface 1 and 2, IEEE Std 1588 77 5 Security Fuse Processor . 153 2.13 USB 84 6 Ordering Information 153 2.14 Enhanced Local Bus Interface .87 6.1 Part Numbering Nomenclature . 153 2.15 Enhanced Secure Digital Host Controller (eSDHC) .92 6.2 Orderable Part Numbers Addressed by This 2.16 Programmable Interrupt Controller (PIC) Specifications94 Document . 154 2.17 JTAG Controller .95 7 Revision History . 156 2 2.18 I C .97 2.19 GPIO 100 P4080/P4081 QorIQ Integrated Processor Hardware Specifications, Rev. 4 2 Freescale Semiconductor