PCA6416A 2 Low-voltage translating 16-bit I C-bus/SMBus I/O expander with interrupt output, reset, and configuration registers Rev. 2. 10 January 2013 Product data sheet 1. General description The PCA6416A is a 16-bit general purpose I/O expander that provides remote I/O 2 expansion for most microcontroller families via the I C-bus interface. NXP I/O expanders provide a simple solution when additional I/Os are needed while keeping interconnections to a minimum, for example, in battery-powered mobile applications for interfacing to sensors, push buttons, keypad, etc. In addition to providing a flexible set of GPIOs, it simplifies interconnection of a processor running at one voltage level to I/O devices operating at a different (usually higher) voltage level. The PCA6416A has built-in level shifting feature that makes these devices extremely flexible in mixed signal environments where communication between incompatible I/O voltages is required. Its wide V range of 1.65 V to 5.5 V on the dual power rail allows seamless DD communications with next-generation low voltage microprocessors and microcontrollers on the interface side (SDA/SCL) and peripherals at a higher voltage on the port side. There are two supply voltages for PCA6416A: V and V . V DD(I2C-bus) DD(P) DD(I2C-bus) provides the supply voltage for the interface at the master side (for example, a microcontroller) and the V provides the supply for core circuits and Port P. The DD(P) bidirectional voltage level translation in the PCA6416A is provided through V . DD(I2C-bus) V should be connected to the V of the external SCL/SDA lines. This indicates DD(I2C-bus) DD 2 the V level of the I C-bus to the PCA6416A. The voltage level on Port P of the DD PCA6416A is determined by the V . DD(P) The PCA6416A register set consists of four pairs of 8-bit Configuration, Input, Output, and Polarity Inversion registers. At power-on, the I/Os are configured as inputs. However, the system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding input or output register. The polarity of the Input Port register can be inverted with the Polarity Inversion register, saving external logic gates. The system master can reset the PCA6416A in the event of a time-out or other improper operation by asserting a LOW in the RESET input. The power-on reset puts the registers 2 in their default state and initializes the I C-bus/SMBus state machine. The RESET pin causes the same reset/initialization to occur without depowering the part. The PCA6416A open-drain interrupt (INT) output is activated when any input state differs from its corresponding Input Port register state and is used to indicate to the system master that an input state has changed.PCA6416A NXP Semiconductors 2 Low-voltage translating 16-bit I C-bus/SMBus I/O expander INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data 2 on its ports without having to communicate via the I C-bus. Thus, the PCA6416A can remain a simple slave device. The device Port P outputs have 25 mA sink capabilities for directly driving LEDs while consuming low device current. 2 One hardware pin (ADDR) can be used to program and vary the fixed I C-bus address 2 and allow up to two devices to share the same I C-bus or SMBus. 2. Features and benefits 2 I C-bus to parallel port expander Operating power supply voltage range of 1.65 V to 5.5 V Allows bidirectional voltage-level translation and GPIO expansion between: 1.8V SCL/SDA and 1.8V, 2.5V, 3.3V or 5V Port P 2.5V SCL/SDA and 1.8V, 2.5V, 3.3V or 5V Port P 3.3V SCL/SDA and 1.8V, 2.5V, 3.3V or 5V Port P 5V SCL/SDA and 1.8V, 2.5V, 3.3V or 5V Port P Low standby current consumption: 1.5 A typical at 5 V V DD 1.0 A typical at 3.3 V V DD Schmitt-trigger action allows slow input transition and better switching noise immunity at the SCL and SDA inputs V = 0.18 V (typical) at 1.8 V hys V = 0.25 V (typical) at 2.5 V hys V = 0.33 V (typical) at 3.3 V hys V = 0.5 V (typical) at 5 V hys 5 V tolerant I/O ports Active LOW reset input (RESET) Open-drain active LOW interrupt output (INT) 2 400 kHz Fast-mode I C-bus Input/Output Configuration register Polarity Inversion register Internal power-on reset Power-up with all channels configured as inputs No glitch on power-up Noise filter on SCL/SDA inputs Latched outputs with 25 mA drive maximum capability for directly driving LEDs Latch-up performance exceeds 100 mA per JESD 78, Class II ESD protection exceeds JESD 22 2000 V Human-Body Model (A114-A) 1000 V Charged-Device Model (C101) Packages offered: TSSOP24, HWQFN24, VFBGA24 PCA6416A All information provided in this document is subject to legal disclaimers. NXP B.V. 2013. All rights reserved. Product data sheet Rev. 2 10 January 2013 2 of 42
