PTN3360D Enhanced performance HDMI/DVI level shifter with active DDC buffer, supporting 3 Gbit/s operation Rev. 4 29 June 2012 Product data sheet 1. General description The PTN3360D is a high-speed level shifter device which converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and HDMI v1.4b compliant open-drain current-steering differential output signals, up to 3.0 Gbit/s per lane to support 36-bit deep color mode, 4K 2K video format or 3D video data transport. Each of these lanes provides a level-shifting differential buffer to translate from low-swing AC-coupled differential signaling on the source side, to TMDS-type DC-coupled differential current-mode signaling terminated into 50 to 3.3 V on the sink side. Additionally, the PTN3360D provides a single-ended active buffer for voltage translation of the HPD signal from 5 V on the sink side to 3.3 V on the source side and provides a channel with active buffering and level shifting of the DDC channel (consisting of a clock and a data line) between 3.3 V source-side and 5 V sink-side. The DDC channel is implemented using 2 active I C-bus buffer technology providing capacitive isolation, redriving and level shifting as well as disablement (isolation between source and sink) of the clock and data lines. The low-swing AC-coupled differential input signals to the PTN3360D typically come from a display source with multi-mode I/O, which supports multiple display standards, for example, DisplayPort, HDMI and DVI. While the input differential signals are configured to carry DVI or HDMI coded data, they do not comply with the electrical requirements of the DVI v1.0 or HDMI v1.4b specification. By using PTN3360D, chip set vendors are able to implement such reconfigurable I/Os on multi-mode display source devices, allowing the support of multiple display standards while keeping the number of chip set I/O pins low. See Figure 1. The PTN3360D main high-speed differential lanes feature low-swing self-biasing differential inputs which are compliant to the electrical specifications of DisplayPort Standard v1.2 and/or PCI Express Standard v1.1, and open-drain current-steering differential outputs compliant to DVI v1.0 and HDMI v1.4b electrical specifications. The 2 I C-bus channel actively buffers as well as level-translates the DDC signals for optimal capacitive isolation. The PTN3360D also supports power-saving modes in order to minimize current consumption when no display is active or connected. The PTN3360D is a fully featured HDMI as well as DVI level shifter. The PTN3360D supersedes PTN3360B, and provides a better high speed performance with a programmable equalizer. PTN3360D is powered from a single 3.3 V power supply consuming a small amount of power (230 mW typical) and is offered in a 48-terminal HVQFN48 package. PTN3360D NXP Semiconductors HDMI/DVI level shifter supporting 3 Gbit/s operation MULTI-MODE DISPLAY SOURCE OE N PTN3360D reconfigurable I/Os PCIe PHY ELECTRICAL AC-coupled OUT D4+ PCIe TMDS differential pair OUT D4 coded output buffer TMDS data TX IN D4+ data FF DATA LANE IN D4 TX AC-coupled OUT D3+ PCIe TMDS differential pair OUT D3 coded output buffer TMDS data TX IN D3+ data FF DATA LANE IN D3 TX AC-coupled OUT D2+ PCIe TMDS differential pair OUT D2 output buffer coded TMDS data TX IN D2+ data FF DATA LANE IN D2 TX AC-coupled OUT D1+ TMDS PCIe differential pair OUT D1 output buffer clock clock TX pattern IN D1+ CLOCK LANE FF IN D1 TX 0 V to 3.3 V 0 V to 5 V HPD SOURCE HPD SINK quinary input EQ5 DDC EN 3.3 V (0 V to 3.3 V) 3.3 V 5 V SCL SOURCE SCL SINK 3.3 V 5 V DDC I/O 2 (I C-bus) SDA SINK CONFIGURATION SDA SOURCE 002aaf240 Remark: TMDS clock and data lanes can be assigned arbitrarily and interchangeably to D 4:1 . Fig 1. Typical application system diagram PTN3360D All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Product data sheet Rev. 4 29 June 2012 2 of 24 DVI/HDMI CONNECTOR