PX1011B
PCI Express stand-alone X1 PHY
Rev. 6 27 June 2011 Product data sheet
1. General description
The PX1011B is a high-performance, low-power, single-lane PCI Express electrical
PHYsical layer (PHY) that handles the low level PCI Express protocol and signaling. The
PX1011B PCI Express PHY is compliant to the PCI Express Base Specification,
Rev. 1.0a, and Rev. 1.1. The PX1011B includes features such as Clock and Data
Recovery (CDR), data serialization and de-serialization, 8b/10b encoding, analog buffers,
elastic buffer and receiver detection, and provides superior performance to the Media
Access Control (MAC) layer devices.
The PX1011B is a 2.5 Gbit/s PCI Express PHY with 8-bit data PXPIPE interface. Its
PXPIPE interface is a superset of the PHY Interface for the PCI Express (PIPE)
specification, enhanced and adapted for off-chip applications with the introduction of a
source synchronous clock for transmit and receive data. The 8-bit data interface operates
at 250 MHz with SSTL_2 signaling. The SSTL_2 signaling is compatible with the I/O
interfaces available in FPGA products.
The PX1011B PCI Express PHY supports advanced power management functions.
The PX1011BI is for the industrial temperature range ( 40 C to +85 C).
Automotive AEC-Q100 compliant version PX1011B-EL1/Q900 is available.
2. Features and benefits
2.1 PCI Express interface
Compliant to PCI Express Base Specification 1.1
Single PCI Express 2.5 Gbit/s lane
Data and clock recovery from serial stream
Serializer and De-serializer (SerDes)
Receiver detection
8b/10b coding and decoding, elastic buffer and word alignment
Supports loopback
Supports direct disparity control for use in transmitting compliance pattern
Supports lane polarity inversion
Low jitter and Bit Error Rate (BER)
2.2 PHY/MAC interface
Based on Intel PHY Interface for PCI Express architecture v1.0 (PIPE)
Adapted for off-chip with additional synchronous clock signals (PXPIPE)
8-bit parallel data interface for transmit and receive at 250 MHz
2.5 V SSTL_2 class I signalingPX1011B
NXP Semiconductors
PCI Express stand-alone X1 PHY
2.3 JTAG interface
JTAG (IEEE 1149.1) boundary scan interface
Built-In Self Test (BIST) controller tests SerDes and I/O blocks at speed
3.3 V CMOS signaling
2.4 Power management
Dissipates < 300 mW in L0 normal mode
Support power management of L0, L0s and L1
2.5 Clock
100 MHz external reference clock with 300 ppm tolerance
Supports spread spectrum clock to reduce EMI
On-chip reference clock termination
2.6 Miscellaneous
LFBGA81 leaded or lead-free packages
Operating ambient temperature
Commercial: 0 C to +70 C
Industrial: 40 C to +85 C
ESD protection voltage for Human Body Model (HBM): 2000 V
3. Quick reference data
Table 1. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
V digital supply voltage 1 for JTAG I/O 3.0 3.3 3.6 V
DDD1
V digital supply voltage 2 for SSTL_2 I/O 2.3 2.5 2.7 V
DDD2
V digital supply voltage 3 for core 1.15 1.2 1.3 V
DDD3
V supply voltage for high-speed 1.15 1.2 1.3 V
DD
serial I/O and PVT
V analog supply voltage 1 for serializer 1.15 1.2 1.3 V
DDA1
V analog supply voltage 2 for serializer 3.0 3.3 3.6 V
DDA2
f reference clock frequency 99.97 100 100.03 MHz
clk(ref)
T ambient temperature operating
amb
commercial 0 - +70 C
industrial 40 - +85 C
PX1011B All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 27 June 2011 2 of 32