S9KEAZN8AMTGR

Document Number S9KEA8P44M48SF0 NXP Semiconductors Rev. 5, 10/2019 Data Sheet: Technical Data S9KEA8P44M48SF0 KEA8 Sub-Family Data Sheet Supports the following: S9KEAZN8ACTG(R), S9KEAZN8ACFK(R), S9KEAZN8AMTG(R) and S9KEAZN8AMFK(R) Key features Security and integrity modules 80-bit unique identification (ID) number per chip Operating characteristics Voltage range: 2.7 to 5.5 V Human-machine interface Flash write voltage range: 2.7 to 5.5 V Up to 57 general-purpose input/output (GPIO) Temperature range (ambient): -40 to 125C Up to 37 general-purpose input/output (GPIO) Up to 22 general-purpose input/output (GPIO) Performance Up to 14 general-purpose input/output (GPIO) Up to 48 MHz Arm Cortex-M0+ core Two up to 8-bit keyboard interrupt modules (KBI) Single cycle 32-bit x 32-bit multiplier External interrupt (IRQ) Single cycle I/O access port Analog modules Memories and memory interfaces One 12-channel 12-bit SAR ADC, operation in Stop Up to 8 KB flash mode, optional hardware trigger (ADC) Up to 1 KB RAM Two analog comparators containing a 6-bit DAC Clocks and programmable reference input (ACMP) Oscillator (OSC) - supports 32.768 kHz crystal or 4 Timers MHz to 24 MHz crystal or ceramic resonator choice One 6-channel FlexTimer/PWM (FTM) of low power or high gain oscillators One 2-channel FlexTimer/PWM (FTM) Internal clock source (ICS) - internal FLL with One 2-channel periodic interrupt timer (PIT) internal or external reference, 37.5 kHz pre-trimmed One pulse width timer (PWT) internal reference for 48 MHz system clock One real-time clock (RTC) Internal 1 kHz low-power oscillator (LPO) Communication interfaces System peripherals One SPI module (SPI) Power management module (PMC) with three power One UART module (UART) modes: Run, Wait, Stop One I2C module (I2C) Low-voltage detection (LVD) with reset or interrupt, selectable trip points Package options Watchdog with independent clock source (WDOG) 24-pin QFN Programmable cyclic redundancy check module 16-pin TSSOP (CRC) Serial wire debug interface (SWD) Aliased SRAM bitband region (BIT-BAND) Bit manipulation engine (BME) NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.Table of Contents 1 Ordering parts.......................................................................................3 4.2.2 FTM module timing....................................................... 15 1.1 Determining valid orderable parts............................................... 3 4.3 Thermal specifications.................................................................16 2 Part identification................................................................................. 3 4.3.1 Thermal characteristics.................................................. 16 2.1 Description...................................................................................3 5 Peripheral operating requirements and behaviors................................ 17 2.2 Format..........................................................................................3 5.1 Core modules............................................................................... 17 2.3 Fields............................................................................................3 5.1.1 SWD electricals .............................................................18 2.4 Example....................................................................................... 4 5.2 External oscillator (OSC) and ICS characteristics.......................19 3 Ratings..................................................................................................4 5.3 NVM specifications..................................................................... 21 3.1 Thermal handling ratings............................................................. 4 5.4 Analog..........................................................................................22 3.2 Moisture handling ratings............................................................ 4 5.4.1 ADC characteristics....................................................... 22 3.3 ESD handling ratings................................................................... 5 5.4.2 Analog comparator (ACMP) electricals.........................24 3.4 Voltage and current operating ratings..........................................5 5.5 Communication interfaces........................................................... 25 4 General................................................................................................. 6 5.5.1 SPI switching specifications.......................................... 25 4.1 Nonswitching electrical specifications........................................ 6 6 Dimensions...........................................................................................28 4.1.1 DC characteristics.......................................................... 6 6.1 Obtaining package dimensions.................................................... 28 4.1.2 Supply current characteristics........................................ 12 7 Pinout................................................................................................... 28 4.1.3 EMC performance..........................................................14 7.1 Signal multiplexing and pin assignments.................................... 28 4.2 Switching specifications.............................................................. 14 8 Revision History...................................................................................29 4.2.1 Control timing................................................................ 14 KEA8 Sub-Family Data Sheet, Rev. 5, 10/2019 2 NXP Semiconductors