Document Number S9S08RN16DS Freescale Semiconductor Rev 1, 02/2014 Data Sheet: Technical Data S9S08RN16DS S9S08RN16 Series Data Sheet Supports: S9S08RN16 and S9S08RN8 Key features Development support Single-wire background debug interface 8-Bit S08 central processor unit (CPU) Breakpoint capability to allow three breakpoints Up to 20 MHz bus at 2.7 V to 5.5 V across setting during in-circuit debugging temperature range of -40 C to 125 C On-chip in-circuit emulator (ICE) debug module Supporting up to 40 interrupt/reset sources containing two comparators and nine trigger Supporting up to four-level nested interrupt modes On-chip memory Up to 16 KB flash read/program/erase over full operating voltage and temperature Up to 256 byte EEPROM with ECC 2-byte erase sector EEPROM program and erase while executing code from flash Up to 2048 byte random-access memory (RAM) Flash and RAM access protection Power-saving modes One low-power stop mode reduced power wait mode Peripheral clock enable register can disable clocks to unused modules, reducing currents allows clocks to remain enabled to specific peripherals in stop3 mode Clocks Oscillator (XOSC) - loop-controlled Pierce oscillator crystal or ceramic resonator Internal clock source (ICS) - containing a frequency-locked-loop (FLL) controlled by internal or external reference precision trimming of internal reference allowing 1% deviation across temperature range of 0 C to 70 C and -40 C to 85 C, 1.5% deviation across temperature range of -40 C to 105 C, and 2% deviation across temperature range of -40 C to 125 C up to 20 MHz System protection Watchdog with independent clock source Low-voltage detection with reset or interrupt selectable trip points Illegal opcode detection with reset Illegal address detection with reset Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 2014 Freescale Semiconductor, Inc. Peripherals ACMP - one analog comparator with both positive and negative inputs separately selectable interrupt on rising and falling comparator output filtering ADC - 12-channel, 12-bit resolution for 48-, 32-pin packages 10-channel, 10-bit resolution for 20-pin package 8-channel, 10-bit for 16-pin package 2.5 s conversion time data buffers with optional watermark automatic compare function internal bandgap reference channel operation in stop mode optional hardware trigger CRC - programmable cyclic redundancy check module FTM - two flex timer modulators modules including one 6-channel and one 2-channel ones 16-bit counter each channel can be configured for input capture, output compare, edge- or center-aligned PWM mode IIC - One inter-integrated circuit module up to 400 kbps multi-master operation programmable slave address supporting broadcast mode and 10-bit addressing MTIM - One modulo timer with 8-bit prescaler and overflow interrupt RTC - 16-bit real time counter (RTC) SCI - two serial communication interface (SCI/UART) modules optional 13-bit break full duplex non-return to zero (NRZ) LIN extension support SPI - one 8-bit serial peripheral interface (SPI) modules full-duplex or single-wire bidirectional master or slave mode TSI - supporting up to 16 external electrodes configurable software or hardware scan trigger fully support freescale touch sensing software library capability to wake MCU from stop3 mode Input/Output Up to 35 GPIOs including one output-only pin One 8-bit keyboard interrupt module (KBI) Two true open-drain output pins Four, ultra-high current sink pins supporting 20 mA source/sink current Package options 48-pin LQFP 32-pin LQFP 20-pin TSSOP 16-pin TSSOP S9S08RN16 Series Data Sheet, Rev1, 02/2014. 2 Freescale Semiconductor, Inc.