S9S12XS256J0VAL NXP

MC9S12XS256 Reference Manual Covers MC9S12XS Family MC9S12XS256 MC9S12XS128 MC9S12XS64 HCS12 Microcontrollers MC9S12XS256RMV1 Rev. 1.13 08/2012 freescale.comTo provide the most up-to-date information, the document revision on the World Wide Web is the most current. A printed copy may be an earlier revision. To verify you have the latest information available, refer to freescale.com. This document contains information for the complete S12XS Family and thus includes a set of separate flash (FTMR) module sections to cover the whole family. A full list of family members and options is included in the appendices. This document contains information for all constituent modules, with the exception of the CPU. For CPU information please refer to CPU12XV1 in the CPU12/CPU12X Reference Manual. Revision History Revision Date Description Level Updated Chapter 3 Memory Mapping Control (S12XMMCV4) Updated Chapter 11 Freescales Scalable Controller Area Network November, (S12MSCANV3) 1.11 2010 Updated Chapter 14 Serial Communication Interface (S12SCIV5) Updated footnotes on table 1-2 Updated note in Appendix F Ordering Information Corrected API accuracy in feature list Corrected name of pin 27 in 80QFP pinout (PE5->PE4) Jul, 2011 1.12 Updated Chapter 2 Port Integration Module (S12XSPIMV1) Updated Chapter 11 Freescales Scalable Controller Area Network (S12MSCANV3) Updated Chapter 4 Interrupt (S12XINTV2) Updated Chapter 8 S12XE Clocks and Reset Generator (S12XECRGV1) Updated V max. voltage in Appendix A Electrical Characteristics DDF Aug, 2012 1.13 Minor editorial corrections in: Chapter 2 Port Integration Module (S12XSPIMV1) Chapter 5 Background Debug Module (S12XBDMV2) Chapter 6 S12X Debug (S12XDBGV3) Module