Freescale Semiconductor Document Number: MPC5606S Rev. 8, 11/2011 Data Sheet: Technical Data MPC5606S MPC5606S Microcontroller Data Sheet LQFP144 (20 x 20 mm) LQFP176 (24 x 24 mm) Includes processing of up to four planes that can be Single issue, 32-bit Power Architecture Book E compliant blended together CPU core complex (e200z0h) Offers a direct unbuffered hardware bit-blitter of up to Compatible with classic PowerPC instruction set 16 software-configurable dynamic layers in order to Includes variable length encoding (VLE) instruction set drastically minimize graphic memory requirements and for smaller code size footprint with the encoding of provide fast animations mixed 16-bit and 32-bit instructions, it is possible to Programmable display resolutions are available up to achieve significant code size footprint reduction over WVGA conventional Book E compliant code Parallel Data Interface (PDI) for digital video input On-chip ECC flash memory with flash controller LCD segment driver module with two software Up to 1 MB primary flashtwo 512 KB modules with programmable configurations: prefetch buffer and 128-bit data access port Up to 40 frontplane drivers and 4 backplane drivers 64 KB data flashseparate 4 16 KB flash block for Up to 38 frontplane drivers and 6 backplane drivers EEPROM emulation with prefetch buffer and 128-bit Stepper Motor Controller (SMC) module with high-current data access port drivers for up to six instrument cluster gauges driven in full Up to 48 KB on-chip ECC SRAM with SRAM controller dual H-Bridge configuration including full diagnostics for Up to 160 KB on-chip non-ECC graphics SRAM with short circuit detection SRAM controller Stepper motor return-to-zero and stall detection module Memory Protection Unit (MPU) with up to 12 region Sound generation and playback utilizing PWM channels descriptors and 32-byte region granularity to provide basic and eDMA supports monotonic and polyphonic sound memory access permission 24 eMIOS channels providing up to 16 PWM and 24 input Interrupt Controller (INTC) with up to 127 peripheral capture / output compare channels interrupt sources and eight software interrupts 10-bit Analog-to-Digital Converter (ADC) 2 Frequency-Modulated Phase-Locked Loops (FMPLLs) Maximum conversion time of 1 s Primary FMPLL provides a 64 MHz system clock Up to 16 internal channels, expandable to 23 via external Auxiliary FMPLL is available for use as an alternate, multiplexing modulated or non-modulated clock source to eMIOS Up to 2 Deserial Serial Peripheral Interface (DSPI) modules and as alternate clock to the DCU for pixel modules for full-duplex, synchronous communications clock generation with external devices (extendable to include up to 8 Crossbar switch architecture enables concurrent access of multiplexed external channels) peripherals, flash memory, or RAM from multiple bus QuadSPI serial flash memory controller supporting single, masters (AMBA 2.0 v6 AHB) dual, and quad modes of operation to interface to external 16-channel Enhanced Direct Memory Access controller serial flash memory QuadSPI can be configured to (eDMA) with multiple transfer request sources using a function as another DSPI module (MPC5606S only) DMA channel multiplexer 2 Local Interconnect Network Flexible (LINFlex) Boot Assist Module (BAM) supports internal flash controller modules capable of autonomous message programming via a serial link (FlexCAN or LINFlex) handling (master), autonomous header handling (slave Display Control Unit to drive TFT LCD displays Freescale Semiconductor, Inc., 20082011. All rights reserved.mode), and UART support compliant with LIN protocol Clock Monitor Unit (CMU) to monitor the integrity of the rev 2.1 main crystal oscillator and the PLL and act as a frequency 2 full CAN 2.0B controllers with 64 configurable buffers meter, measuring the frequency of one clock source and each bit rate programmable up to 1 Mbit/s comparing it to a reference clock 2 Up to 4 Inter-integrated circuit (I C) internal bus Mode Entry Module (MC ME) to control the device controllers with master/slave bus interface power mode, in other words, Run, Halt, Stop, or Standby Up to 133 configurable general purpose pins supporting control mode transition sequences, and manage the power input and output operations control, voltage regulator, clock generation, and clock Real Time Counter (RTC) with multiple clock sources: management modules 128 kHz slow internal RC oscillator or 16 MHz fast Reset Generation Module (MC RGM) to manage reset internal RC oscillator supporting autonomous wakeup assertion and release to the device at initial startup with 1 ms resolution with maximum timeout of 2 Nexus development interface (NDI) per IEEE-ISTO seconds 5001-2003 Class Two Plus standard 32 kHz slow external crystal oscillator, supporting Device/board boundary-scan testing supported per Joint wakeup with 1 s resolution and maximum timeout of Test Action Group (JTAG) of IEEE (IEEE 1149.1) one hour On-chip voltage regulator controller for regulating the 3.3 416 MHz fast external crystal oscillator or 5 V supply voltage down to 1.2 V for core logic System timers: (requires external ballast transistor) 4-channel 32-bit System Timer Module The MPC5606S microcontrollers are offered in the 1 (STM)included in processor platform following packages: 4-channel 32-bit Periodic Interrupt Timer (PIT) module 144 LQFP, 0.5 mm pitch, 20 mm 20 mm outline Software Watchdog Timer (SWT) 176 LQFP, 0.5 mm pitch, 24 mm 24 mm outline System Integration Unit (SIU) module to manage resets, 208 MAPBGA, 1.0 mm pitch, 17 mm 17 mm outline external interrupts, GPIO, and pad control (not a production package available in limited System Status and Configuration Module (SSCM) to quantities for tool development only) provide information for identification of the device, last boot mode, or debug status, and provides an entry point for the censorship password mechanism Clock Generation Module (MC CGM) to generate system 1. See the device comparison table or orderable parts clock sources and provide a unified register interface, summary for package offerings for each device in the family. enabling access to all clock sources MPC5606S Microcontroller Data Sheet, Rev. 8 2 Freescale Semiconductor