Document Number MPC5746C NXP Semiconductors Rev. 6, 11/2018 Data Sheet: Technical Data MPC5746C MPC5746C Microcontroller Datasheet Features 32-channel eDMA controller with multiple transfer request sources using DMAMUX 1 160 MHz Power Architecture e200z4 Dual issue, 32-bit CPU Boot Assist Flash (BAF) supports internal flash Single precision floating point operations programming via a serial link (SCI) 8 KB instruction cache and 4 KB data cache Analog Variable length encoding (VLE) for significant code Two analog-to-digital converters (ADC), one 10-bit density improvements and one 12-bit 1 x 80 MHz Power Architecture e200z2 Single issue, Three analog comparators 32-bit CPU Cross Trigger Unit to enable synchronization of Using variable length encoding (VLE) for ADC conversions with a timer event from the significant code size footprint reduction eMIOS or from the PIT End to end ECC Communication All bus masters, for example, cores, generate a Four Deserial Serial Peripheral Interface (DSPI) single error correction, double error detection Four Serial Peripheral interface (SPI) (SECDED) code for every bus transaction 16 serial communication interface (LIN) modules SECDED covers 64-bit data and 29-bit address Eight enhanced FlexCAN3 with FD support Four inter-IC communication interface (I2C) Memory interfaces ENET complex (10/100 Ethernet) that supports 3 MB on-chip flash memory supported with the Multi queue with AVB support, 1588, and MII/ flash memory controller RMII 3 x flash memory page buffers (3-port flash memory Dual-channel FlexRay controller controller) 384 KB on-chip SRAM across three RAM ports Audio Synchronous Audio Interface (SAI) Clock interfaces Fractional clock dividers (FCD) operating in 8-40 MHz external crystal (FXOSC) conjunction with the SAI 16 MHz IRC (FIRC) 128 KHz IRC (SIRC) Configurable I/O domains supporting FlexCAN, 32 KHz external crystal (SXOSC) LINFlexD, Ethernet, and general I/O Clock Monitor Unit (CMU) Supports wake-up from low power modes via the Frequency modulated phase-locked loop (FMPLL) WKPU controller Real Time Counter (RTC) On-chip voltage regulator (VREG) System Memory Protection Unit (SMPU) with up to 32 region descriptors and 16-byte region granularity Debug functionality e200z2 core:NDI per IEEE-ISTO 5001-2008 16 Semaphores to manage access to shared resources Class3+ Interrupt controller (INTC) capable of routing e200z4 core: NDI per IEEE-ISTO 5001-2008 Class interrupts to any CPU 3+ Crossbar switch architecture for concurrent access to peripherals, flash memory, and RAM from multiple bus masters NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. Timer 16 Periodic Interrupt Timers (PITs) Two System Timer Modules (STM) Three Software Watchdog Timers (SWT) 64 Configurable Enhanced Modular Input Output Subsystem (eMIOS) channels Device/board boundary Scan testing supported with Joint Test Action Group (JTAG) of IEEE 1149.1 and IEEE 1149.7 (CJTAG) Security Hardware Security Module (HSMv2) Password and Device Security (PASS) supporting advanced censorship and life-cycle management One Fault Collection and Control Unit (FCCU) to collect faults and issue interrupts Functional Safety ISO26262 ASIL-B compliance Multiple operating modes Includes enhanced low power operation MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 2 NXP Semiconductors