QorIQ Communications Platforms T Seriesi.MX 6SoloX QorIQ T2080 and T2081applications processors communication and could be on prtwo linesocessors The 28 nm QorIQ T2080 and T2081 communications processors bring the architectural innovations of the T series flagship T4240, such as the 1.8 GHz dual-threaded e6500 core, into an eight virtual core mid-range platform at reduced power and price points. OVERVIEW achieves up to 1.8 GHz even while maintaining a short seven- stage pipeline for better latency response to unpredictable The T2080 processor is primarily intended to succeed our control plane code branches. Advanced virtualization successful P3041 and P2041 mid-range series of quad-core technology facilitates safe partitioning of control and data devices as a control plane or integrated control and data plane applications within the device. plane processor. It provides an excellent migration path, as it offers 2x or better in core capability, cache size, SerDes Enterprise equipment: Modular Ethernet switches, services bandwidth and Ethernet connectivity within a similar power cards, UTM equipment, enterprise storage, data center budget. It also provides a value engineering opportunity for Service pr ovider: Core and edge routers, broadband P4080 customers, as T2080 provides equivalent performance access, metro Ethernet, optical networking at much lower price and power. Wireless infrastructure: Mobile backhaul, NICs, channel The T2081 is a smaller package version of the T2080, which cards, control cards in LTE, WCDMA, GSM, WiMAX is pin compatible with the quad-core T1042. This provides Aerospace and defense: ruggedized or highly secure T1042 customers an easy upgrade to higher performance routers, avionics networking, instrumentation panels, if processing requirements increase. It also enables customers military SBCs to reuse a single board for two different product performance levels. Industrial computing: SBCs, factory automation, test and measurement TARGET MARKETS AND APPLICATIONS The T2080 and T2081 processors are targeted at mid-range control plane applications or mixed control and data plane applications. The highly efficient eight virtual core device E6500 CORE QorIQ T2080 COMMUNICATIONS PROCESSOR The T2080 and T2081 processors are based on the 64-bit e6500 core, built T1 T2 T1 T2 T1 T2 T1 T2 Power Power Power Power on Power Architecture technology, and e6500 e6500 e6500 e6500 run up to 1.8 GHz. The e6500 core also 32 KB 32 KB 32 KB 32 KB 32 KB 32 KB 32 KB 32 KB D-Cache I-Cache D-Cache I-Cache D-Cache I-Cache D-Cache I-Cache offers higher aggregate instructions per 64-bit DDR3/3L 512KB Platform Cache Memory Controller 2MB Banked L2 clock at lower power with an innovative fused core approach to threading. Security Fuse Processor Coherency Fabric Security Monitor The e6500s fully resourced dual threads PAMU PAMU Peripheral Access Mgmt Unit PAMU IFC provide 1.7 times the performance of a Power Management Real-Time Debug Security Parse, Classify, Distribute 5.2 Queue DCE single thread. SDXC/eMMC 8ch 8ch 8ch Warchpoint (XoR, 1.0 Mgr. DMA DMA DMA Cross Trigger HiGig/+ DCB CRC) 2x DUART The four e6500 dual-threaded cores 2 4x I C Perf. CoreNet Frame Manager Monitor Trace PME Buffer RMan SPI, GPIO share a low-latency backside 2 MB L2 2.1 Mgr. 4x 1 / 2.5 / 10G 4x 1 / 2.5G Aurora 2x USB2.0 + PHY cache, allowing efficient sharing of code 8-Lane 10 GHz SerDes 8-Lane 8 GHz SerDes and data. Each e6500 core implements the NXP AltiVec technology-based Core Complex Complex (CPU, L2, L3 Cache) Basic Peripherals and Interconnect SIMD engine, dramatically boosting the Accelerators and Memory Control Networking Elements performance of media and networking algorithms, offering native inline programming and using less power than T2080 VS. T2081 DIFFERENCES a separate DSP. T2080 T2081 VIRTUALIZATION TThe T2080 and T2081 processors SerDes 16 8 include support for hardware-assisted PCIe 2x Gen3 + 2x Gen2 1x Gen3 + 3x Gen2 virtualization. The e6500 core offers an extra core privilege level (hypervisor) SRIO 2 + RMan No and hardware offload of logical to real address translation. In addition, the SATA 2 No T2080 and T2081 include platform- level enhancements such as SR-IOV and Aurora Yes No I/O virtualization with DMA memory protection through IOMMUs and 10 Gb/s MACs Up to four, with XFI, XAUI, HiGig Up to 2x XFI configurable storage profiles, which provide isolation of I/O buffers between 1 Gb/s MACs Up to eight Up to seven guest environments. Virtualization 23 x 23mm, 780 pins, 0.8 mm pitch, Package 25 x 25mm, 896 pins, 0.8 mm pitch software for the T2080 and T2081 pin compatible with T1042 processors includes kernel virtualization model (KVM), Linux containers and the NXP hypervisor. DATA PATH ACCELERATION and congestion management. The FMAN ARCHITECTURE (DPAA) passes its work to the QMAN, which assigns it to cores or accelerators with The T2080 and T2081 processors a multi-level scheduling hierarchy, while integrate the QorIQ DPAA, an innovative maintaining packet ordering. The BMAN multicore infrastructure for scheduling manages allocation and de-allocation work to cores (physical and virtual), of packet buffers. The T2080 and hardware accelerators and network T2081s implementation of DPAA offers interfaces. The FMAN, a primary element accelerators for cryptography, deep of the DPAA, parses headers from packet inspection and compression incoming packets and classifies and decompression. selects data buffers with optional policing PCle PCle Pre-fetch PCle PCle sRIO sRIO SAT A 2.0 SAT A 2.0