UJA1168 Mini high-speed CAN system basis chip for partial networking Rev. 2 16 April 2014 Product data sheet 1. General description The UJA1168 is a mini high-speed CAN System Basis Chip (SBC) containing an ISO 11898-2/5/6 compliant HS-CAN transceiver and an integrated 5 V/100 mA supply for a microcontroller. It also features a watchdog and a Serial Peripheral Interface (SPI). The UJA1168 can be operated in very low-current Standby and Sleep modes with bus and local wake-up capability and supports ISO 11898-6 compliant CAN partial networking by means of a selective wake-up function. The microcontroller supply is switched off in Sleep mode. The UJA1168TK and UJA1168TK/FD versions contain a battery-related high-voltage output (INH) for controlling an external voltage regulator, while the UJA1168TK/VX and UJA1168TK/VX/FD are equipped with a 5 V sensor supply (VEXT). A dedicated implementation of the partial networking protocol has been embedded into the UJA1168/FD variants, UJA1168TK/FD and UJA1168TK/VX/FD (see Section 6.8.1 for further details on CAN FD). This function is called FD-passive and is the ability to ignore CAN FD frames while waiting for a valid wake-up frame in Sleep/Standby mode. This additional feature of partial networking is the perfect fit for networks that support both CAN FD and standard CAN 2.0 communications. It allows normal CAN controllers that do not need to communicate CAN FD messages to remain in partial networking Sleep/Standby mode during CAN FD communication without generating bus errors. The UJA1168 implements the standard CAN physical layer as defined in the current ISO11898 standard (-2, -5 and -6). Pending the release of the updated version of ISO11898 including CAN FD, additional timing parameters defining loop delay symmetry are included. This implementation enables reliable communication in the CAN FD fast phase at data rates up to 2 Mbit/s. A number of configuration settings are stored in non-volatile memory, allowing the SBC to be adapted for use in a specific application. This makes it possible to configure the power-on behavior of the UJA1168 to meet the requirements of different applications. 2. Features and benefits 2.1 General ISO 11898-2, ISO 11898-5 and ISO 11898-6 compliant high-speed CAN transceiver Loop delay symmetry timing enables reliable communication at data rates up to 2 Mbit/s in the CAN FD fast phase Autonomous bus biasing according to ISO 11898-6 Fully integrated 5 V/100 mA low-drop voltage regulator for 5 V microcontroller supply (V1) Bus connections are truly floating when power to pin BAT is offUJA1168 NXP Semiconductors Mini high-speed CAN system basis chip for partial networking No false wake-ups due to CAN FD frame detection in UJA1168TK/FD and UJA1168TK/VX/FD 2.2 Designed for automotive applications 8 kV ElectroStatic Discharge (ESD) protection, according to the Human Body Model (HBM) on the CAN bus pins 6 kV ESD protection, according to IEC 61000-4-2 on the CAN bus pins, the sensor supply output VEXT and on pins BAT and WAKE CAN bus pins short-circuit proof to 58 V Battery and CAN bus pins protected against automotive transients according to ISO 7637-3 Very low quiescent current in Standby and Sleep modes with full wake-up capability Leadless HVSON14 package (3.0 mm 4.5 mm) with improved Automated Optical Inspection (AOI) capability and low thermal resistance Dark green product (halogen free and Restriction of Hazardous Substances (RoHS) compliant) 2.3 Low-drop voltage regulator for 5 V microcontroller supply (V1) 5 V nominal output 2 % accuracy 100 mA output current capability Current limiting above 150 mA On-resistance of 5 (max) Support for microcontroller RAM retention down to a battery voltage of 2 V Undervoltage reset with selectable detection thresholds: 60 %, 70 %, 80 % or 90 % of output voltage Excellent transient response with a 4.7 F ceramic output capacitor Short-circuit to GND/overload protection on pin V1 Turned off in Sleep mode 2.4 Power Management Standby mode featuring very low supply current voltage V1 remains active to maintain the supply to the microcontroller Sleep mode featuring very low supply current with voltage V1 switched off Remote wake-up capability via standard CAN wake-up pattern or via ISO 11898-6 compliant selective wake-up frame detection Local wake-up via the WAKE pin Wake-up source recognition Local and/or remote wake-up can be disabled to reduce current consumption High-voltage output (INH) for controlling an external voltage (UJA1168TK and UJA1168TK/FD) 2.5 System control and diagnostic features Mode control via the Serial Peripheral Interface (SPI) Overtemperature warning and shutdown Watchdog with independent clock source UJA1168 All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2 16 April 2014 2 of 68