74AC251 74ACT251 8-Input Multiplexer with 3-STATE Output November 1988 Revised November 1999 74AC251 74ACT251 8-Input Multiplexer with 3-STATE Output General Description Features The AC/ACT251 is a high-speed 8-input digital multiplexer. I reduced by 50% CC It provides, in one package, the ability to select one bit of Multifunctional capability data from up to eight sources. It can be used as universal On-chip select logic decoding function generator to generate any logic function of four Inverting and noninverting 3-STATE outputs variables. Both true and complementary outputs are pro- vided. Outputs source/sink 24 mA ACT251 has TTL-compatible inputs Ordering Code: Order Number Package Number Package Description 74AC251SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Body 74AC251SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74AC251MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74AC251PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 74ACT251SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Body 74ACT251MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACT251PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names Description S S Select Inputs 0 2 OE 3-STATE Output Enable Input I I Multiplexer Inputs 0 7 Z 3-STATE Multiplexer Output Z Complementary 3-STATE Multiplexer Output FACT is a trademark of Fairchild Semiconductor Corporation. 1999 Fairchild Semiconductor Corporation DS009945 www.fairchildsemi.comFunctional Description Truth Table This device is a logical implementation of a single-pole, 8- Inputs Outputs position switch with the switch position controlled by the state of three Select inputs, S , S , S . Both true and com- 0 1 2 OE S S S Z Z 2 1 0 plementary outputs are provided. The Output Enable input H X X X Z Z (OE) is active LOW. When it is activated, the logic function provided at the output is: L L L L I I 0 0 Z = OE (I S S S + I S S S + 0 0 1 2 1 0 1 2 L L L H I I 1 1 I S S S + I S S S + 2 0 1 2 3 0 1 2 L L H L I I 2 2 I S S S + I S S S + 4 0 1 2 5 0 1 2 L L H H I I 3 3 I S S S + I S S S ) 6 0 1 2 7 0 1 2 L H L L I I When the Output Enable is HIGH, both outputs are in the 4 4 high impedance (High Z) state. This feature allows multi- L H L H I I 5 5 plexer expansion by tying the outputs of up to 128 devices L H H L I I together. When the outputs of the 3-STATE devices are 6 6 tied together, all but one device must be in the high imped- L H H H I I 7 7 ance state to avoid high currents that would exceed the H = HIGH Voltage Level maximum ratings. The Output Enable signals should be L = LOW Voltage Level designed to ensure there is no overlap in the active-LOW X = Immaterial portion of the enable voltages. Z = High Impedance Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 74AC251 74ACT251