74F164APC ON Semiconductor

74F164A Serial-In, Parallel-Out Shift Register October 1989 Revised October 2000 74F164A Serial-In, Parallel-Out Shift Register General Description Features The 74F164A is a high-speed 8-bit serial-in/parallel-out Typical shift frequency of 90 MHz shift register. Serial data is entered through a 2-input AND Asynchronous Master Reset gate synchronous with the LOW-to-HIGH transition of the Gated serial data input clock. The device features an asynchronous Master Reset Fully synchronous data transfers which clears the register, setting all outputs LOW indepen- dent of the clock. The 74F164A is a faster version of the 74F164A is a faster version of the 74F164 74F164. Ordering Code: Order Number Package Number Package Description 74F164ASC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 74F164ASJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F164APC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code. Logic Symbols Connection Diagram IEEE/IEC 2000 Fairchild Semiconductor Corporation DS010613 www.fairchildsemi.comUnit Loading/Fan Out U.L. Input I /I IH IL Pin Names Description Output I /I HIGH/LOW OH OL A, B Data Inputs 1.0/1.0 20 A/0.6 mA CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 A/0.6 mA MR Master Reset Input (Active LOW) 1.0/1.0 20 A/0.6 mA Q Q Outputs 50/33.3 1 mA/20 mA 0 7 Functional Description Mode Select Table The 74F164A is an edge-triggered 8-bit shift register with Operating Inputs Outputs serial data entry and an output from each of the eight stages. Data is entered serially through one of two inputs Q Q Q Mode MR AB 0 1 7 (A or B) either of these inputs can be used as an active Reset (Clear) L X X L L-L HIGH Enable for data entry through the other input. An Hl l L q q 0 6 unused input must be tied HIGH. Shift H l h L q q Each LOW-to-HIGH transition on the Clock (CP) input 0 6 shifts data one place to the right and enters into Q the log- Hh l L q q 0 0 6 ical AND of the two data inputs (A B) that existed before Hh h H q q 0 6 the rising clock edge. A LOW level on the Master Reset H(h) = HIGH Voltage Levels (MR) input overrides all other inputs and clears the register L(l) = LOW Voltage Levels asynchronously, forcing all Q outputs LOW. X = Immaterial q = Lower case letters indicate the state of the referenced input or output n one setup time prior to the LOW-to-HIGH clock transition. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 74F164A