74LVT16952 74LVTH16952 Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs
January 2000
Revised October 2001
74LVT16952 74LVTH16952
Low Voltage 16-Bit Registered Transceiver
with 3-STATE Outputs
General Description Features
The LVT16952 and LVTH16952 are 16-bit registered Input and output interface capability to systems at
transceivers. Two 8-bit back to back registers store data 5V V
CC
flowing in both directions between two bidirectional buses.
Bushold data inputs eliminate the need for external
Separate clock, clock enable, and output enable signals
pull-up resistors to hold unused inputs (74LVTH16952)
are provided for each register.
Live insertion/extraction permitted
The LVTH16952 data inputs include bushold, eliminating
Power Up/Down high impedance provides glitch-free
the need for external pull-up resistors to hold unused
bus loading
inputs.
Outputs source/sink 32 mA/+64 mA
The registered transceiver is designed for low-voltage
Functionally compatible with the 74 series 16952
(3.3V) V applications, but with the capability to provide a
CC
Latch-up conforms to JEDEC JED78
TTL interface to a 5V environment.
ESD performance:
The LVT16952 and LVTH16952 are fabricated with an
advanced BiCMOS technology to achieve high speed oper-
Human-body model > 2000V
ation similar to 5V ABT while maintaining low power dissi-
Machine model > 200V
pation.
Charged-device model > 1000V
Ordering Code:
Order Number Package Number Package Description
74LVT16952MEA MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
(Preliminary)
74LVT16952MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
(Preliminary)
74LVTH16952MEA MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LVTH16952MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.
2001 Fairchild Semiconductor Corporation DS500103 www.fairchildsemi.comConnection Diagram Pin Descriptions
Pin Names Description
A A Data Register A Inputs
0 16
B-Register 3-STATE Outputs
B B Data Register B Inputs
0 16
A-Register 3-STATE Outputs
CPAB , CPBA Clock Pulse Inputs
n n
CEA , CEB Clock Enable
n n
OEAB , OEBA Output Enable Inputs
n n
Truth Table
(Note 1)
Inputs Internal Register Output
A CPAB CEA OEAB Value B
n n n n n
XX H L NC B
0
XX H H NC Z
L LL L L
L LH L Z
H LL H H
H LH H Z
XL X L NC B
0
XH X L NC B
0
XL X H NC Z
XH X H NC Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = Output High Impedance
= LOW-to-HIGH Transition.
NC = No Change (state established by last valid CP)
B = State established by last valid CP
0
Note 1: A to B data flow shown; B to A flow control is the same, but used
OEBA , CPBA and CEB .
n n n
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74LVT16952 74LVTH16952