74LVX157MX ON Semiconductor

74LVX157 Low Voltage Quad 2-Input Multiplexer May 1993 Revised October 2003 74LVX157 Low Voltage Quad 2-Input Multiplexer General Description Features The LVX157 is a high-speed quad 2-input multiplexer. Four Input voltage level translation from 5V to 3V bits of data from two sources can be selected using the Ideal for low power/low noise 3.3V applications common Select and Enable inputs. The four outputs Guaranteed simultaneous switching noise level and present the selected data in the true (noninverted) form. dynamic threshold performance The LVX157 can also be used as a function generator. Ordering Code: Order Number Package Number Package Description 74LVX157M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74LVX157SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVX157MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices are also available in Tape and Reel. Specify by appending letter suffix X to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names Description I I Source 0 Data Inputs 0a 0d I I Source 1 Data Inputs 1a 1d E Enable Input S Select Input Z Z Outputs a d 2003 Fairchild Semiconductor Corporation DS011608 www.fairchildsemi.comTruth Table Inputs Outputs E SI I Z 0 1 HX X X L LH X L L LH X H H LL L X L LL H X H H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Functional Description The LVX157 is a quad 2-input multiplexer. It selects four A common use of the LVX157 is the moving of data from bits of data from two sources under the control of a com- two groups of registers to four common output busses. The mon Select input (S). The Enable input (E) is active-LOW. particular register from which the data comes is determined When E is HIGH, all of the outputs (Z) are forced LOW by the state of the Select input. A less obvious use is as a regardless of all other inputs. The LVX157 is the logic function generator. The LVX157 can generate any four of implementation of a 4-pole, 2-position switch where the the sixteen different functions of two variables with one position of the switch is determined by the logic levels sup- variable common. This is useful for implementing gating plied to the Select input. The logic equations for the outputs functions. are shown below: Z = E (I S + I S) a 1a 0a Z = E (I S + I S) b 1b 0b Z = E (I S + I S) c 1c 0c Z = E (I S + I S) d 1d 0d Logic Diagram www.fairchildsemi.com 2 74LVX157