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This literature is subject to all applicable copyright laws and is not for resale in any manner.74VHC573 Octal D-Type Latch with 3-STATE Outputs May 2007 74VHC573 tm Octal D-Type Latch with 3-STATE Outputs Features General Description High Speed: t = 5.0ns (Typ.) at V = 5V The VHC573 is an advanced high speed CMOS octal PD CC latch with 3-STATE output fabricated with silicon gate High Noise Immunity: V = V = 28% V (Min.) NIH NIL CC CMOS technology. It achieves the high speed operation Power Down Protection is provided on all inputs similar to equivalent Bipolar Schottky TTL while main- Low Noise: V = 0.6V (Typ.) OLP taining the CMOS low power dissipation. This 8-bit Low Power Dissipation: I = 4A (Max.) T = 25C CC A D-type latch is controlled by a latch enable input (LE) Pin and function compatible with 74HC573 and an Output Enable input (OE ). When the OE input is HIGH, the eight outputs are in a high impedance state. An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mis- matched supply and input voltages. Ordering Information Order Number Package Package Description Number 74VHC573M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74VHC573SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHC573MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter X to the ordering number. Pb-Free package per JEDEC J-STD-020B. Connection Diagram Pin Description Pin Names Description D D Data Inputs 0 7 LE Latch Enable Input 3-STATE Output Enable Input OE O O 3-STATE Outputs 0 7 1993 Fairchild Semiconductor Corporation www.fairchildsemi.com 74VHC573 Rev. 1.3