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This literature is subject to all applicable copyright laws and is not for resale in any manner.74VHCT08A Quad 2-Input AND Gate February 2008 74VHCT08A Quad 2-Input AND Gate Features General Description High speed: t = 5.0ns (typ.) at T = 25C The VHCT08A is an advanced high speed CMOS 2 PD A Input AND Gate fabricated with silicon gate CMOS tech- High noise immunity: V = 2.0V, V = 0.8V IH IL nology. It achieves the high-speed operation similar to Power down protection is provided on all inputs and equivalent Bipolar Schottky TTL while maintaining the outputs CMOS low power dissipation. Low noise: V = 0.8V (max.) OLP The internal circuit is composed of 4 stages including Low power dissipation: I = 2A (max.) T = 25C CC A buffer output, which provide high noise immunity and Pin and function compatible with 74HCT08 stable output. Protection circuits ensure that 0V to 7V can be applied to the input pins without regard to the supply voltage and to the output pins with V = 0V. These circuits prevent CC device destruction due to mismatched supply and input/ output voltages. This device can be used to interface 3V to 5V systems and two supply systems such as battery backup. Ordering Information Package Order Number Number Package Description 74VHCT08AM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74VHCT08ASJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHCT08AMTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74HCT08AN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. 1997 Fairchild Semiconductor Corporation www.fairchildsemi.com 74VHCT08A Rev. 1.3.0