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This literature is subject to all applicable copyright laws and is not for resale in any manner.74VHCT573A Octal D-Type Latch with 3-STATE Outputs May 2007 74VHCT573A tm Octal D-Type Latch with 3-STATE Outputs Features General Description High speed: t = 7.7ns (Typ.) at T = 25C The VHCT573A is an advanced high speed CMOS octal PD A latch with 3-STATE output fabricated with silicon gate High Noise Immunity: V = 2.0V, V = 0.8V IH IL CMOS technology. It achieves the high speed operation Power Down Protection is provided on all inputs and similar to equivalent Bipolar Schottky TTL while main- outputs taining the CMOS low power dissipation. This 8-bit Low Noise: V = 1.6V (Max.) OLP D-type latch is controlled by a Latch Enable input (LE) Low Power Dissipation: I = 4A (Max.) T = 25C CC A and an Output Enable input (OE ). When the OE input is Pin and function compatible with 74HCT573 HIGH, the eight outputs are in a high impedance state. Protection circuits ensure that 0V to 7V can be applied to (1) the input and output pins without regard to the supply voltage. This device can be used to interface 3V to 5V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mis- matched supply and input voltages. Note: 1. Outputs in OFF-State Ordering Information Package Order Number Number Package Description 74VHCT573AM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74VHCT573ASJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHCT573AMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter X to the ordering number. Pb-Free package per JEDEC J-STD-020B. Connection Diagram Pin Description Pin Names Description D D Data Inputs 0 7 LE Latch Enable Input 3-STATE Output Enable Input OE O O 3-STATE Outputs 0 7 1997 Fairchild Semiconductor Corporation www.fairchildsemi.com 74VHCT573A Rev. 1.3