74VHCT573AFT(BE) Toshiba

74VHCT573AFT CMOS Digital Integrated Circuits Silicon Monolithic 74VHCT573AFT74VHCT573AFT74VHCT573AFT74VHCT573AFT 1. 1. Functional DescriptionFunctional Description 1. 1. Functional DescriptionFunctional Description Octal D-Type Latch with 3-State Outputs 2. 2. 2. 2. GeneralGeneralGeneralGeneral The 74VHCT573A is an advanced high speed CMOS OCTAL LATCH with 3-STATE OUTPUT fabricated with silicon gateC2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type latch is controlled by a latch enable input (LE) and an output enable input (OE).When the OE input is high, the eight outputs are in a high impedance state. The input voltage are compatible with TTL output voltage. This device may be used as a level converter for interfacing 3.3V to 5 V system. Input protection and output circuit ensure that 0 to 5.5 V can be applied to the input and output (Note) pins without regard to the supply voltage. These structure prevents device destruction due to mismatched supply and input/output voltages such as battery back up, hot board insertion, etc. Note: Output in off-state 3. 3. FeaturesFeatures 3. 3. FeaturesFeatures (1) AEC-Q100 (Rev. H) (Note 1) (2) Wide operating temperature range: T = -40 to 125 opr (3) High speed: Propagation delay time = 7.7 ns (typ.) at V = 5.0 V CC (4) Low power dissipation: I = 4.0 A (max) at T = 25 CC a (5) Compatible with TTL inputs: V = 0.8 V (max) IL V = 2.0 V (min) IH (6) Power down protection is provided on all inputs and outputs. (7) Balanced propagation delays: t t PLH PHL (8) Low noise: V = 1.5 V (max) OLP (9) Pin and function compatible with the 74 series (74ACT/HCT/AHCT etc.) 573 type. Note 1: This device is compliant with the reliability requirements of AEC-Q100. For details, contact your Toshiba sales representative. 4. 4. 4. 4. PackagingPackagingPackagingPackaging TSSOP20B Start of commercial production 2013-04 2016 Toshiba Corporation 2016-08-04 1 Rev.3.074VHCT573AFT 5. 5. 5. 5. Pin AssignmentPin AssignmentPin AssignmentPin Assignment 6. 6. 6. 6. MarkingMarkingMarkingMarking 7. 7. 7. 7. IEC Logic SymbolIEC Logic SymbolIEC Logic SymbolIEC Logic Symbol 2016 Toshiba Corporation 2016-08-04 2 Rev.3.0