74VHCV07FT(BJ) Toshiba

74VHCV07FT CMOS Digital Integrated Circuits Silicon Monolithic 74VHCV07FT74VHCV07FT74VHCV07FT74VHCV07FT 1. 1. Functional DescriptionFunctional Description 1. 1. Functional DescriptionFunctional Description Hex Schmitt Buffer (Open Drain) 2. 2. 2. 2. GeneralGeneralGeneralGeneral The 74VHCV07FT is an advanced high speed CMOS BUFFER fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. Output have high performance MOS N-channel transistor. (OPEN-DRAIN outputs) Input pin have hysteresis between the positive-going and negative-going thresholds. Thus the 74VHCV07FT is capable of squaring up transitions of slowly changing input signals such as line receivers. Input protection and output circuit ensure that 0 to 5.5 V can be applied to the input and output pins without regard to the supply voltage. These structure prevents device destruction due to mismatched supply and input/ output voltages such as battery back up, etc. 3. 3. FeaturesFeatures 3. 3. FeaturesFeatures (1) AEC-Q100 (Rev. H) (Note 1) (2) Wide operating temperature range: T = -40 to 125 opr (3) High speed: t = 3.8 ns (typ.) at V = 5.0 V pd CC (4) Low power dissipation: I = 2.0 A (max) at T = 25 CC a (5) Wide operating voltage range: V = 1.8 V to 5.5 V CC(opr) (6) Output current: I = 16 mA (min)(V = 4.5 V) OL CC (7) Power-down protection is provided on all inputs and outputs. (8) Pin and function compatible with the 74 series (74AC/HC/AHC/LV etc.) 07 type. Note 1: This device is compliant with the reliability requirements of AEC-Q100. For details, contact your Toshiba sales representative. 4. 4. 4. 4. PackagingPackagingPackagingPackaging TSSOP14B Start of commercial production 2014-11 2016 Toshiba Corporation 2016-08-04 1 Rev.2.074VHCV07FT 5. 5. 5. 5. Pin AssignmentPin AssignmentPin AssignmentPin Assignment 6. 6. 6. 6. MarkingMarkingMarkingMarking 7. 7. 7. 7. Truth TableTruth TableTruth TableTruth Table A Y L L H Z 8. 8. System Diagram (per gate)System Diagram (per gate) 8. 8. System Diagram (per gate)System Diagram (per gate) 2016 Toshiba Corporation 2016-08-04 2 Rev.2.0