ADP3120AJRZ-RL ON Semiconductor

ADP3120A Dual Bootstrapped, 12 V MOSFET Driver with Output Disable The ADP3120A is a single Phase 12 V MOSFET gate drivers optimized to drive the gates of both highside and lowside power www.onsemi.com MOSFETs in a synchronous buck converter. The highside and MARKING lowside driver is capable of driving a 3000 pF load with a 45 ns DIAGRAMS propagation delay and a 25 ns transition time. 8 With a wide operating voltage range, high or low side MOSFET 3120A SO8 gate drive voltage can be optimized for the best efficiency. Internal ALYW D SUFFIX 8 adaptive nonoverlap circuitry further reduces switching losses by CASE 751 1 preventing simultaneous conduction of both MOSFETs. 1 The floating top driver design can accommodate VBST voltages as 1 8 high as 35 V, with transient voltages as high as 40 V. Both gate outputs DFN8 L3C MN SUFFIX can be driven low by applying a low logic level to the Output Disable ALYW CASE 506BJ 1 (OD) pin. An Undervoltage Lockout function ensures that both driver outputs are low when the supply voltage is low, and a Thermal Shutdown function provides the IC with overtemperature protection. A = Assembly Location L = Wafer Lot Features Y = Year W = Work Week AllInOne Synchronous Buck Driver = PbFree Package Bootstrapped HighSide Drive One PWM Signal Generates Both Drives PIN CONNECTIONS Anticross Conduction Protection Circuitry 18 BST DRVH OD for Disabling the Driver Outputs Meets CPU VR Requirement IN SWN when Used with Patented FlexMode Controller OD PGND These are PbFree Devices V DRVL CC Applications 18 Multiphase Desktop CPU Supplies BST DRVH SingleSupply Synchronous Buck Converters IN SWN OD PGND V DRVL CC (Top View) ORDERING INFORMATION Device Package Shipping ADP3120AJRZ SO8 98 Units / Rail (PbFree) ADP3120AJRZRL SO8 2500 / Tape & (PbFree) Reel ADP3120AJCPZRL DFN8 3000 / Tape & (PbFree) Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2012 1 Publication Order Number: August, 2018 Rev. 5 ADP3120A/DADP3120A 3 OD V TSD CC BST 1 UVLO 2 DRVH IN 8 FALLING EDGE MONITOR DELAY 7 SWN FALLING EDGE MONITOR DELAY START STOP NONOVERLAP 4 V MIN DRVL CC TIMERS OFF TIMER 5 DRVL 6 PGND Figure 1. Block Diagram PIN DESCRIPTION SO8 DFN8 Symbol Description 1 1 BST Upper MOSFET Floating Bootstrap Supply. A capacitor connected between BST and SW pins holds this bootstrap voltage for the highside MOSFET as it is switched. The recommended capacitor value is between 100 nF and 1.0 F. An external diode is required with the ADP3120A. 2 2 IN LogicLevel Input. This pin has primary control of the drive outputs. 3 3 OD Output Disable. When low, normal operation is disabled forcing DRVH and DRVL low. 4 4 V Input Supply. A 1.0 F ceramic capacitor should be connected from this pin to PGND. CC 5 5 DRVL Output drive for the lower MOSFET. 6 6 PGND Power Ground. Should be closely connected to the source of the lower MOSFET. 7 7 SWN Switch Node. Connect to the source of the upper MOSFET. 8 8 DRVH Output drive for the upper MOSFET. www.onsemi.com 2