5 4 3 2 1 AR0237 iBGA80 Demo3Head D D Page Description 1 Title Page 2 Block Diagram 3 Sensor 4 Power 5 Clock and Reset 6 External Interfaces Rev Who Date Description Rev 0.0 aralex 06/10/15 Initial schematic taken from AR0230 IBGA 80 demo3 HB design because the pinout is the same. Changed P3 from 2 pin header to 3 pin header Added R50, P30 Deleted R8 C C 06/12/15 Updated with the new Sensor part for AR0237 B B A A TTTiiitttllleee TTTIIITTTLLLEEE PPPAAAGGGEEE SSSiiizzzeee DDDooocccuuummmeeennnttt NNNaaammmeee RRReeevvv CCC AAARRR000222333777---BBBGGGAAA888000 DDDeeemmmooo333HHHeeeaaaddd 000 DDDaaattteee::: FFFrrriiidddaaayyy,,, JJJuuunnneee 111222,,, 222000111555 SSShhheeeeeettt 111 ooofff 666 5 4 3 2 1VDD-SLVS +1V8 HB +1V2 HB VAA-PIX +2V8 VAA HB VAA VPP Headers VAAHV NPIX VDD-PHY +1V8 HB VDD +2V8 VDDIO HB VDD-PLL +VDDIO VDDIO SENSE +3V3 HB 5 4 3 2 1 Block Diagram D D 52-Pin Demo3 Connector (QFS) 0.4V Reg +3.3V +VDDIO LS DEMO3 CLK +VDDIO LS HB MCLK C C +VDDIO LS Clock +3.3V S CLK Select Headers OSC (27MHz) HISPI CLK P/N HISPI DATA(3:0) P/N HB RST N +3.3V S RST N MR RESET (240ms) +VDDIO LS SENSOR - AR0237 iBGA80 ATEST Header SADDR 0:0x20,1:0x30 SIGNAL TEST Headers PAR OE N TRIGGER S DOUT(11:0) B B Output FLASH Headers SHUTTER S FV S LV CONTROL SIGNALS SP1 - SADDR SP2 - TEST SP3 - PAR OE N S PIXCLK SP4 - TRIGGER DEMO I2C SENSOR I2C +VDDIO LS EEPROM 64kbit 0xA8 (default) A A TTTiiitttllleee BBBLLLOOOCCCKKK DDDIIIAAAGGGRRRAAAMMM SSSiiizzzeee DDDooocccuuummmeeennnttt NNNaaammmeee RRReeevvv CCC AAARRR000222333777---BBBGGGAAA888000 DDDeeemmmooo333HHHeeeaaaddd 000 DDDaaattteee::: FFFrrriiidddaaayyy,,, JJJuuunnneee 111222,,, 222000111555 SSShhheeeeeettt 222 ooofff 666 5 4 3 2 1