AR0330CM
1/3inch CMOS
Digital Image Sensor
Description
The AR0330 from ON Semiconductor is a 1/3-inch CMOS digital
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image sensor with an active-pixel array of 2304 (H) 1536 (V). It can
support 3.15 Mp (2048 (H) 1536 (V)) digital still image capture and
a 1080p60 + 20% EIS (2304 (H) 1296 (V)) digital video mode. It
incorporates sophisticated on-chip camera functions such as
windowing, mirroring, column and row sub-sampling modes, and
snapshot modes.
CLCC48 ODCSP64
CASE 848AU CASE 570BH
Table 1. KEY PERFORMANCE PARAMETERS
Parameter Typical Value
ORDERING INFORMATION
Optical Format 1/3-inch (6.0 mm)
See detailed ordering and shipping information on page 2 of
Entire Array: 6.09 mm
this data sheet.
Still Image: 5.63 mm (4:3)
HD Image: 5.82 mm (16:9)
Features
Active Pixels 2304 (H) 1536 (V): (Entire Array)
5.07mm (H) 3.38mm (V)
2.2m Pixel with APix Technology
2048 (H) 1536 (V) (4:3, Still Mode)
2304 (H) 1296 (V) (16:9, HD Mode) Full HD support at 60 fps
(2304 (H) 1296 (V)) for Maximum
Pixel Size
2.2 2.2 m
Video Performance
Color Filter Array RGB Bayer
Superior Low-light Performance
Shutter Type ERS and GRR
3.4 Mp (3:2) and 3.15 Mp (4:3) Still Images
Input Clock Range 627 MHz
Support for External Mechanical Shutter
Output Clock Maximum 196 Mp/s (4-lane HiSPi or MIPI)
Support for External LED or Xenon Flash
Output Video 4-lane HiSPi 2304 1296 at 60 fps
Data Interfaces: Four-lane Serial High-speed
< 450 mW (V 0.2 V, 198 MP/s)
CM
Pixel Interface (HiSPi) Differential
2304 1296 at 30 fps
Signaling (SLVS), Four-lane Serial MIPI
< 300 mW (V 0.2 V, 98 MP/s)
CM
Interface, or Parallel
2.0 V/luxsec
Responsivity
On-chip Phase-locked Loop (PLL)
SNR 39 dB
MAX
Oscillator
Dynamic Range 69.5 dB
Simple Two-wire Serial Interface
Supply Voltage Auto Black Level Calibration
Digital 1.71.9 V (1.8 V Nominal)
12-to-10 Bit Output ALaw Compression
Analog 2.72.9 V
HiSPi PHY 1.71.9 V (1.8 V Nominal)
Slave Mode for Precise Frame-rate Control
HiSPi I/O (SLVS) 0.30.9 V (0.4 or 0.8 V Nominal)
and for Synchronizing Two Sensors
HiSPi I/O (HiVCM) 1.71.9 V (1.8 V Nominal)
I/O/Digital 1.71.9 V (1.8 V Nominal) or
Applications
2.43.1 V (2.8 V Nominal)
1080p High-definition Digital Video
Operating Temperature 30C to + 70C
Camcorder
(Junction) T
J
Web Cameras and Video Conferencing
Package Options CLCC 11.4 mm 11.4mm
CSP 6.28 mm 6.65 mm Cameras
Bare Die
Security
Semiconductor Components Industries, LLC, 2010
1 Publication Order Number:
March, 2017 Rev. 18 AR0330CM/DAR0330CM
ORDERING INFORMATION
Table 2. AVAILABLE PART NUMBERS
Part Number Product Description Orderable Product Attribute Description
AR0330CM1C00SHAA0DP 3 MP 1/3 CIS Dry Pack with Protective Film
AR0330CM1C00SHAA0DR 3 MP 1/3 CIS Dry Pack without Protective Film
AR0330CM1C00SHAA0TP 3 MP 1/3 CIS Tape & Reel with Protective Film
AR0330CM1C00SHKA0CP 3 MP 1/3 CIS Chip Tray with Protective Film
AR0330CM1C00SHKA0CR 3 MP 1/3 CIS Chip Tray without Protective Film
AR0330CM1C12SHAA0DP 3 MP 1/3 CIS Dry Pack with Protective Film
AR0330CM1C12SHAA0DR 3 MP 1/3 CIS Dry Pack without Protective Film
AR0330CM1C12SHKA0CP 3 MP 1/3 CIS Chip Tray with Protective Film
AR0330CM1C12SHKA0CR 3 MP 1/3 CIS Chip Tray without Protective Film
AR0330CM1C21SHKA0CP 3 MP 1/3 CIS Chip Tray with Protective Film
AR0330CM1C21SHKA0CR 3 MP 1/3 CIS Chip Tray without Protective Film
GENERAL DESCRIPTION FUNCTIONAL OVERVIEW
The AR0330 can be operated in its default mode or
The AR0330 is a progressive-scan sensor that generates
programmed for frame size, exposure, gain, and other
a stream of pixel data at a constant frame rate. It uses an
parameters. The default mode output is a 2304 1296 image
on-chip, phase-locked loop (PLL) that can generate all
at 60 frames per second (fps). The sensor outputs 10- or
internal clocks from a single master input clock running
12-bit raw data, using either the parallel or serial (HiSPi,
between 6 and 27 MHz. The maximum output pixel rate is
MIPI) output ports.
196 Mp/s using a 4-lane HiSPi or MIPI serial interface and
98 Mp/s using the parallel interface.
Test Pattern
Ext
Generator
Clock
12-bit
Analog Core
Digital Core Output Data-Path
Row Noise Correction Compression (Optional)
PLL
Black Level Correction
Digital Gain
Timing
Column
Pixel
and
Data Pedestal
Amplifiers
Array
Control
12-bit 10- or 12-bit
12-bit
ADC
Registers 8-,
12-bit
10-
or 12-bit
Two-wire
Serial I/F Parallel I/O: MIPI I/O: HiSPi I/O:
PIXCLK, FV, CLK P/N, SLVS C P/N,
LV, D [11:0] DATA[11:0] P/N SLVS[3:0] P/N
OUT
Figure 1. Block Diagram
User interaction with the sensor is through the two-wire controlled by varying the time interval between reset and
serial bus, which communicates with the array control, readout. Once a row has been read, the signal from the
analog signal chain, and digital signal chain. The core of the column is amplified in a column amplifier and then digitized
sensor is a 3.4 Mp active-pixel sensor array. The timing and in an analog-to-digital converter (ADC). The output from
control circuitry sequences through the rows of the array, the ADC is a 12-bit value for each pixel in the array.
resetting and then reading each row in turn. In the time The ADC output passes through a digital processing signal
interval between resetting a row and reading that row, the chain (which provides further data path corrections and
pixels in the row integrate incident light. The exposure is applies digital gain).
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2
Row Drivers