BelaSigna 300 Audio Processor for Portable Communication Devices Introduction BelaSigna 300 is a DSPbased mixedsignal audio processing system that delivers superior audio clarity without compromising size www.onsemi.com or battery life. The processor is specifically designed for monaural portable communication devices requiring high performance audio processing capabilities and programming flexibility when formfactor and power consumption are key design constraints. The efficient dualMAC 24bit CFX DSP core, together with the HEAR configurable accelerator signal processing engine, high speed debugging interface, advanced algorithm security system, stateof theart analog front end, Class D output stage and much more, DFN44 WLCSP35 constitute an entire system on a single chip, which enables D SUFFIX W SUFFIX CASE 506BU CASE 567AG manufacturers to create a range of advanced and unique products. The system features a high level of instructional parallelism, providing highly efficient computing capability. It can simultaneously execute MARKING DIAGRAM multiple advanced adaptive noise reduction and echo cancellation algorithms, and uses an asymmetric dualcore patented architecture to allow for more processing in fewer clock cycles, resulting in reduced BELASIGNA300 3502G power consumption. XXXXYZZ BelaSigna 300 is supported by a comprehensive suite of development tools, handson training, full technical support and a BELASIGNA300 = Device Code network of solution partners offering software and engineering 35 = Number of Balls services to help speed product design and shorten time to market. 02 = Revision of Die G = PbFree Key Features XXXX = Date Code Y = Assembly Plant Identifier Flexible DSPbased System: a complete DSPbased, mixedsignal = (May be Two Characters) audio system consisting of the CFX core, a fully programmable, ZZ = Traceability Code highly cycleefficient, dualHarvard architecture 24bit DSP utilizing explicit parallelism the HEAR configurable accelerator for optimized signal processing and an efficient input/output controller ORDERING INFORMATION (IOC) along with a full complement of peripherals and interfaces, Device Package Shipping which optimize the architecture for audio processing at extremely low power consumption B300W35A109XXG WLCSP 2500 / Tape & (PbFree) Reel Ultralowpower: typically 15 mA B300D44A103XXG DFN 2500 / Tape & Excellent Audio Fidelity: up to 110 dB input dynamic range, (PbFree) Reel exceptionally low system noise and low group delay For information on tape and reel specifications, in- Miniature Form Factor: available in a miniature 3.63 mm x cluding part orientation and tape sizes, please refer 2.68 mm x 0.92 mm (including solder balls) WLCSP package. In to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. addition, BelaSigna 300 is also available in a bigger DFN package allowing easier assembly and PCB routing Multiple Audio Input Sources: four input channels from five input sources (depends on package selection) can be used simultaneously for multiple microphones or direct analog audio inputs 2 Full Range of Configurable Interfaces: including a fast I Cbased interface for download, debug and general communication, a highly configurable PCM interface to stream data into and out of the device, a highspeed UART, an SPI port and 5 GPIOs Semiconductor Components Industries, LLC, 2015 1 Publication Order Number: February, 2015 Rev. 8 B300/DBelaSigna 300 Integrated A/D Converters and Powered Output: Data Security: sensitive program data can be minimize need for external components encrypted for storage in external NVRAM to prevent unauthorized parties from gaining access to proprietary Flexible Clocking Architecture: supports speeds up to software intellectual property, 128bit AES encryption 40 MHz Development Tools: interface hardware with USB Smart Power Management: including low current support as well as a full IDE that can be used for every standby mode requiring only 0.06 mA step of program development including testing and Diverse Memory Architecture: 4864x48bit words of debugging shared memory between the CFX core and the HEAR These Devices are PbFree, Halogen Free/BFR Free accelerator plus 8Kword DSP core data memory, and are RoHS Compliant 12Kwords of 32bit DSP core program memory as well as other memory banks Contents Introduction .................................................................................... 1 Figures and Data ................................................................................. 3 Mechanical Information and Circuit Design Guidelines .................................................. 6 Architecture Overview ........................................................................... 12 Application Diagrams ........................................................................... 25 Assembly Information ........................................................................... 27 Miscellaneous .................................................................................. 29 www.onsemi.com 2