DATA SHEET www.onsemi.com Bluetooth 5 Radio System-on-Chip (SoC) WLCSP51 CASE 567MT RSL10 Introduction RSL10 is an ultralowpower, highly flexible multiprotocol 1 48 2.4GHz radio specifically designed for use in highperformance QFN48 wearable and medical applications. With its Arm Cortex M3 CASE 485BA Processor and LPDSP32 DSP core, RSL10 supports Bluetooth low energy technology and 2.4 GHz proprietary protocol stacks, without sacrificing power consumption. Key Features RSL10 RSL10 Rx Sensitivity (Bluetooth Low Energy Mode, 1 Mbps): 94 dBm AWLYWW AWLYYWWG Data Rate: 62.5 to 2000 kbps Transmitting Power: 17 to +6 dBm (QFN48) (WLCSP51) Peak Rx Current = 5.6 mA (1.25 V VBAT) XXXXXX = Specific Device Code Peak Rx Current = 3.0 mA (3 V VBAT) A = Assembly Location Peak Tx Current (0 dBm) = 8.9 mA (1.25 V VBAT) WL = Wafer Lot Y or YY = Year Peak Tx Current (0 dBm) = 4.6 mA (3 V VBAT) WW = Work Week Bluetooth 5 Certified G or = PbFree Package Support for Bluetooth 5 features: LE 2Mbit PHY (High Speed), as well as backwards compatibility and support for earlier Bluetooth Low Energy specifications ORDERING INFORMATION Arm CortexM3 Processor Clocked at up to 48 MHz Device Package Shipping LPDSP32 for Audio Codec NCHRSL10 WLCSP51 5000 / Tape & Supply Voltage Range: 1.1 3.3 V 101WC51ABG (PbFree) Reel Current Consumption (1.25 V VBAT): NCHRSL10 QFN48 3000 / Tape & Deep Sleep, IO Wakeup: 50 nA 101Q48ABG (PbFree) Reel Deep Sleep, 8 kB RAM Retention: 300 nA For information on tape and reel specifications, Audio Streaming at 7 kHz Audio BW: 1.8 mA RX, 1.8 mA TX including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Current Consumption (3 V VBAT): Brochure, BRD8011/D. Deep Sleep, IO Wakeup: 25 nA Deep Sleep, 8 kB RAM Retention: 100 nA Audio Streaming at 7 kHz Audio BW: 0.9 mA RX, 0.9 mA TX 384 kB of Flash Memory Highlyintegrated SystemonChip (SoC) Supports FOTA (Firmware OverTheAir) Updates Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: August, 2021 Rev. 6 RSL10/DRSL10 FEATURES Arm CortexM3 Processor: A 32bit core for Flexible Supply Voltage: RSL10 integrates high realtime applications, specifically developed to enable efficiency power regulators and has a VBAT range of highperformance lowcost platforms for a broad range 1.1 to 3.3 V. See Table 2. RECOMMENDED of lowpower applications. OPERATING CONDITIONS. 2 LPDSP32: A 32bit Dual Harvard DSP core that Highly Configurable Interfaces: I C, UART, two SPI efficiently supports audio codecs required for wireless interfaces, PCM interface, multiple GPIOs. It also audio communication. Various codecs are available to supports a digital microphone interface (DMIC) and an customers through libraries that are included in output driver (OD). RSL10s development tools. The Asynchronous Sample Rate Converter (ASRC) Radio Frequency FrontEnd: Based on a 2.4 GHz RF Block and Audio Sink Clock Blocks: Provides a transceiver, the RFFE implements the physical layer of means of synchronizing the audio sample rate between the Bluetooth low energy technology standard and other an audio source and an audio sink. The audio sink clock proprietary or custom protocols. also provides a high accuracy mechanism to measure an input clock used for the RTC or protocol timing. Protocol Baseband Hardware: Bluetooth 5 certified and includes support for a 2 Mbps RF link and custom Flexible Clocking Scheme: RSL10 must be clocked protocol options. The RSL10 baseband stack is from the XTAL/PLL of the radio frontend at 48 MHz supplemented by support structures that enable when transmitting or receiving RF traffic. When RSL10 implementation of onsemi and customer designed is not transmitting/receiving RF traffic, it can run off custom protocols. the 48 MHz XTAL, the internal RC oscillators, the 32 kHz oscillator, or an external clock. A low HighlyIntegrated SoC: The dualcore architecture is frequency RTC clock at 32 kHz can also be used in complemented by highefficiency power management Deep Sleep Mode. It can be sourced from either the units, oscillators, flash and RAM memories, a DMA internal XTAL, the RC oscillator, or a digital input pad. controller, along with a full complement of peripherals Diverse Memory Architecture: 76 kB of SRAM and interfaces. program memory (4 kB of which is PROM containing Deep Sleep Mode: RSL10 can be put into a Deep the chip bootup program, and is thus unavailable to Sleep Mode when no operations are required. Various the user) and 88 kB of SRAM data memory are Deep Sleep Mode configurations are available, available. A total of 384 kB of flash is available to store including: the Bluetooth stack and other applications. The Arm IO wakeup configuration. The power CortexM3 processor can execute from SRAM and/or consumption in deep sleep mode is 50 nA (1.25 V flash. VBAT). Security: AES128 encryption hardware block for Embedded 32 kHz oscillator running with interrupts from timer or external pin. The total current drain is custom secure algorithms and code protection with 90 nA (1.25 V VBAT). authenticated debug port access (JTAG lock) As above with 8 kB RAM data retention. The total UltraLow Power Consumption Application current drain is 300 nA (1.25 V VBAT). Examples: The DCDC converter can be used in buck mode or Audio Signal Streaming: IDD = 1.8 mA VBAT LDO mode during Sleep Mode, depending on VBAT 1.25 V in Rx Mode for receiving, decoding and voltage. sending an 7 kHz bandwidth audio signal to the SPI Standby Mode: Can be used to reduce the average interface using a proprietary custom audio protocol power consumption for offduty cycle operation, from onsemi. ranging typically from a few ms to a few hundreds of Low Duty Cycle Advertising: IDD 1.1 A for ms. The typical chip power consumption is 30 A in advertising at all three channels at 5 second intervals Standby Mode. VBAT 3 V, DCDC converter enabled. MultiProtocol Support: Using the flexibility RoHS Compliant Device provided by LPDSP32, the Arm CortexM3 processor, and the RF frontend proprietary protocols and other custom protocols are supported. www.onsemi.com 2