CAT28F020L90 ON Semiconductor

CAT28F020 Licensed Intel 2 Megabit CMOS Flash Memory second source FEATURES Commercial, industrial and automotive Fast read access time: 90/120 ns temperature ranges Low power CMOS dissipation: Stop timer for program/erase Active: 30 mA max (CMOS/TTL levels) On-chip address and data latches Standby: 1 mA max (TTL levels) JEDEC standard pinouts: Standby: 100 A max (CMOS levels) 32-pin DIP High speed programming: 32-pin PLCC 10 s per byte 32-pin TSOP (8 x 20) 4 seconds typical chip program 100,000 program/erase cycles 0.5 seconds typical chip-erase 10 year data retention 12.0V 5% programming and erase voltage Electronic signature DESCRIPTION using a two write cycle scheme. Address and Data are The CAT28F020 is a high speed 256K x 8-bit electrically latched to free the I/O bus and address bus during the erasable and reprogrammable Flash memory ideally write operation. suited for applications requiring in-system or after-sale code updates. Electrical erasure of the full memory The CAT28F020 is manufactured using Catalysts contents is achieved typically within 0.5 second. advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data It is pin and Read timing compatible with standard 2 retention of 10 years. The device is available in JEDEC EPROM and E PROM devices. Programming and approved 32-pin plastic DIP, 32-pin PLCC or 32-pin Erase are performed through an operation and verify TSOP packages. algorithm. The instructions are input via the I/O bus, BLOCK DIAGRAM I/O I/O 0 7 I/O BUFFERS ERASE VOLTAGE SWITCH WE DATA SENSE COMMAND PROGRAM VOLTAGE CE, OE LOGIC LATCH AMP REGISTER SWITCH CE OE Y-GATING Y-DECODER 2,097,152 BIT A A 0 17 MEMORY X-DECODER ARRAY VOLTAGE VERIFY 5115 FHD F02 SWITCH 2009 SCILLC. All rights reserved. Doc. No. MD-1029, Rev. F 1 Characteristics subject to change without notice ADDRESS LATCHCAT28F020 PIN CONFIGURATION PIN FUNCTIONS DIP Package (L) PLCC Package (N, G) Pin Name Type Function A A Input Address Inputs for V 1 32 V 0 17 PP CC memory addressing A 2 31 WE 16 A 3 30 A 15 17 4321 323130 I/O I/O I/O Data Input/Output 0 7 A 4 29 A 5 29 A A 12 14 7 14 CE Input Chip Enable A 5 28 A 6 28 A A 7 13 6 13 A 6 27 A 7 27 A A 6 8 5 8 OE Input Output Enable A 7 26 A 8 26 A A 5 9 4 9 WE Input Write Enable A 8 25 A 9 25 A A 4 11 3 11 A 9 24 OE 10 24 A OE 3 2 V Voltage Supply CC A 10 23 A 11 23 A A 2 10 1 10 V Ground A 11 22 CE 12 22 SS A CE 1 0 A 12 21 I/O 13 21 I/O I/O 0 7 0 7 V Program/Erase PP 14 15 16 17 18 19 20 I/O 13 20 I/O 0 6 Voltage Supply I/O 14 19 I/O 1 5 I/O 15 18 I/O 2 4 V 16 17 I/O SS 3 5115 FHD F01 TSOP Package (Standard Pinout) (T, H) A 1 32 OE 11 A 2 31 A 9 10 3 30 CE A 8 4 29 A I/O 13 7 5 28 A I/O 14 6 6 27 A I/O 17 5 7 26 WE I/O 4 8 25 V I/O CC 3 9 24 V V PP SS 10 23 A I/O 16 2 11 22 A I/O 15 1 12 21 A I/O 12 0 13 20 A A 7 0 A 14 19 A 6 1 A 15 18 A 5 2 A 16 17 A 4 3 TSOP Package (Reverse Pinout) (TR, HR) A OE 1 32 11 A 31 A 2 10 9 CE 3 30 A 8 I/O 4 29 A 7 13 5 28 A I/O 6 14 6 27 A I/O 5 17 7 26 WE I/O 4 8 25 V I/O 3 CC 9 24 V V SS PP 10 23 A I/O 2 16 11 22 A I/O 1 15 12 21 A I/O 0 12 13 20 A A 0 7 14 19 A A 1 6 15 18 A A 5 2 16 17 A A 4 3 5115 FHD F14 2009 SCILLC. All rights reserved. Doc. No. MD-1029, Rev. F 2 Characteristics subject to change without notice I/O A 1 12 I/O A 2 15 V A SS 16 I/O V 3 PP I/O V 4 CC I/O WE 5 I/O A 6 17