DM74ALS138 3 to 8 Line Decoder/Demultiplexer
September 1986
Revised February 2000
DM74ALS138
3 to 8 Line Decoder/Demultiplexer
General Description Features
These Schottky-clamped circuits are designed to be used Designed specifically for high speed:
in high-performance memory-decoding or data-routing
Memory decoders
applications, requiring very short propagation delay times.
Data transmission systems
In high-performance memory systems these decoders can
3- to 8-line decoder incorporates 3 enable inputs to sim-
be used to minimize the effects of system decoding. When
plify cascading and/or data reception
used with high-speed memories, the delay times of these
Low power dissipation23 mW typ
decoders are usually less than the typical access time of
the memory. This means that the effective system delay
Switching specifications guaranteed over full tempera-
introduced by the decoder is negligible.
ture and V range
CC
The DM74ALS138 decodes one-of-eight lines, based upon
Advanced oxide-isolated, ion-implanted Schottky TTL
the conditions at the three binary select inputs and the
process
three enable inputs. Two active-LOW and one active-HIGH
enable inputs reduce the need for external gates or invert-
ers when expanding. A 24-line decoder can be imple-
mented with no external inverters, and 32-line decoder
requires only one inverter. An enable input can be used as
a data input for demultiplexing applications.
This decoder/demultiplexer features fully buffered inputs,
presenting only one normalized load to its driving circuit. All
inputs are clamped with high-performance Schottky diodes
to suppress line-ringing and simplify system design.
Ordering Code:
Order Number Package Number Package Description
DM74ALS138M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74ALS138SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74ALS138N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.
Connection Diagram Function Table
Enable Select
Outputs
Inputs Inputs
G1 G2 C B A Y0 Y1 Y2Y3Y4 Y5Y6Y7
(Note 1)
X H X X X HH HHH HHH
L X X X X HH HHH HHH
H L L L L L H HHH HHH
H L L L HH L HHH HHH
H L L H L H H L HH HHH
H L L H HHH H L H HHH
H L HL L H H H HL H H H
H L H L HHH HHH L H H
H L HH L H H HHH H L H
H L HH HHH HHH HH L
Note 1: G2 = G2A + G2B
2000 Fairchild Semiconductor Corporation DS006111 www.fairchildsemi.comLogic Diagram
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DM74ALS138