FAN1655 3A DDR Bus Termination Regulator January 2006 FAN1655 3A DDR Bus Termination Regulator Description Features The FAN1655 is a low-cost bi-directional LDO Sinks and sources 2.1A continuous, 3A peak specically designed for terminating DDR memory bus. It 0 to +125C operating temperature range can both sink and source up to 2.1A continuous, 3A 5mA Buffered VREFOUT = VDDQ/2 peak, providing enough current for most DDR appli- Load regulation: VTT = VREFOUT 40mV cations. Load regulation meets the JEDEC spec, VTT = On-chip thermal limiting VREFOUT 40mV. Low Cost SO-14, Power-Enhanced eTSSOP or The FAN1655 includes a buffered reference voltage 8-pin 5x6mm MLP packages capable of supplying up to 5mA current. On-chip thermal Low-Current Shutdown Mode limiting provides protection against a combination of Output Short Circuit Protection power overload and ambient temperature that would create an excessive junction temperature. A shutdown Applications input puts the FAN1655 into a low power mode. DDR Terminator VTT supply The FAN1655 regulator is available in a power-enhanced eTSSOP-16, standard SOIC-14, and an 8-Lead MLP package. Ordering Information Part Number Temperature Range Package Packing FAN1655M 0C to 125C SOIC-14 Rails FAN1655MX 0C to 125C SOIC-14 Tape and Reel FAN1655MTF 0C to 125C eTSSOP-16 Rails FAN1655MTFX 0C to 125C eTSSOP-16 Tape and Reel FAN1655MPX 0C to 125C MLP-8 Tape and Reel Block Diagram VDDQ VDD VDD VDD SHDN 200k VREFOUT + VTTFORCE + VREFIN VTTFORCE 200k VTTSENSE FAN1655 VSS VSS VSS VSSQ 2006 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com FAN1655 Rev. 1.1.5FAN1655 3A DDR Bus Termination Regulator Pin Assignments VDD 14 VDDQ VDD 16 NC 1 1 VREFOUT VDDQ VDD 2 13 VDD 2 15 VTTFORCE 3 12 VSSQ VTTFORCE 14 VREFOUT 3 VSS FAN1655M VSSQ 4 11 SHDN VSS 4 13 FAN1655 VSS VREFIN VSS 5 SHDN 5 10 12 9 VTTSENSE VTTFORCE 6 11 VREFIN VTTFORCE 6 7 10 VTTSENSE VDD 7 8 VSS VDD 8 9 VSS NC 14-Lead Plastic SOIC 16-Lead Plastic eTSSOP-16 = 37C/W, = 88C/W JC JA = 4C/W* JC *Thermal impedance is measured with the power pad soldered to a 0.5 square inch copper area. The copper area should be connected to Vss (ground) and positioned over an internal power or ground plane to assist in heat dissipation. VDD 1 8 VDDQ VTTFORCE 2 7 VREFOUT VTTFORCE 3 6 SHDN VDD 4 5 VTTSENSE GND 8-Lead MLP Package (5x6mm) = 4C/W, = 34C/W JC JA as measured on FAN1655MP Eval Board Pin Denitions Pin MLP eTSSOP SOIC-14 Pin Name Pin Function 1, 4 1, 2, 7 1, 2, 7 VDD Input power for the LDO. 2, 3 3, 6 3, 6 VTTFORCE The VTT output voltage. PAD 4, 5, 8 4, 5, 8 VSS IC Ground. 5109 VTTSENSE Feedback for remote sense of the VTT voltage. 11 10 VREFIN Alternative input for direct control of VTTOUT and VREFOUT. 61211 SHDN Shutdown. This active low shutdown turns off both VTT and VREFOUT. This pin has an internal pull-down, and must be externally driven high for the IC to be on. 13 12 VSSQ Signal Ground. 71413 VREFOUT Buffered Voltage Reference Output. 81514 VDDQ VDDQ Input. Attach this pin to the VDDQ supply to generate VTT and VREFOUT. 9, 16 NC No Internal Connection PADPAD Connect PAD to Vss Ground Plane 2 www.fairchildsemi.com FAN1655 Rev. 1.1.5