FAN25801 250 mA, Low-I , Low-Noise, LDO Regulator Q GND May 2014 FAN25801 250 mA, Low-I , Low-Noise, LDO Regulator Q Features Description V : 2.3 V to 5.5 V IN The FAN25801 is a linear low-dropout regulator with a high PSRR (80 dB typical at 100 Hz) and low output V = 5.14 V (I Max. = 250 mA) OUT OUT noise (typically 10 V over a 10 Hz to 100 kHz RMS Output Noise Density at 250 mA and bandwidth). The LDO can provide up to 250 mA of 10 kHz = 20 nV/Hz (Integrated 10 Vrms) output current. Low I of 17 A in Regulation and Low-I Dropout Q Q The enable control pin can be used to shut down the Mode with Optimized Dropout Transitions device and disconnect the output load from the input. During shutdown, the supply current drops below 1 A. <70 mV Dropout Voltage at 250 mA Load The FAN25801 is designed to be stable with space- Controlled Soft-Start to Reduce Inrush Current saving ceramic capacitors as small as 0201 case size. Thermal Shutdown Protection (TSD) The FAN25801 is available in a 4-bump, 0.35 mm pitch, WLCSP package. Input Under-Voltage Lockout (UVLO) Short-Circuit Protection (SCP) Stable with Two 1.5 F, 0201 Ceramic Capacitors VIN at VOUT 1.5F FAN25801 VOUT 4-Ball WLCSP, 0.65 mm x 0.65 mm, 0.35 mm Pitch, Plated Solder, 330 m Maximum Thickness 1.5F 1.5F EN Applications WiFi Modules PDA Handsets Figure 1. Typical Application Smart Phones, Tablets, Portable Devices Ordering Information I Operating Packing OUT Part Number V Package OUT Max. Temperature Method 4-Bump, WLCSP, FAN25801AUC514X 5.14 V 250 mA -40C to 85C 0.65 x 0.65 mm, 0.35 mm Tape & Reel Pitch 2014 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN25801 Rev. 1.0.2 FAN25801 250 mA, Low-I , Low-Noise, LDO Regulator Q Block Diagram VIN VOUT C IN C OUT FILTER V REF EN GND Figure 2. IC and System Block Diagram Table 1. Recommended External Components Component Description Vendor Parameter Typ. Unit (1) C 1.5 F, 6.3 V, X5R, 0201 Murata GRM033R60J155M 1.5 F IN (1) C 2x1.5 F, 6.3 V, X5R, 0201 Murata GRM033R60J155M C 1.5 F OUT (2) (1) C 1.0 F, 6.3 V, X5R, 0201 Murata GRM033R60J105M 1.0 F Alternative Notes: 1. Capacitance value does not reflect effects of bias, tolerance, and temperature. See Recommended Operating Conditions and Operation Description sections for more information. 2. C can be used for both C and C . FAN25801 is stable with one 1 F at C and one 1 F at C . Alternative IN OUT IN OUT Pin Configuration VIN A1 A2 VOUT VOUT A2 A1 VIN B1 B1 B2 GND B2 EN EN GND Figure 3. Top-Through View Figure 4. Bottom View Pin Definitions Pin Name Description A1 VIN Input Voltage. Connect to input power source and C . IN A2 VOUT Output Voltage. Connect to C and load. OUT Enable. The device is in Shutdown Mode when this pin is LOW. No internal pull-down. B1 EN (3) Do not leave this pin floating. Recommended to not tie EN pin directly to VIN. B2 GND Ground. Power and IC ground. All signals are referenced to this pin. Note: 3. EN can be tied to VIN, but it is recommended to tie a 1.8 V logic voltage to drive it. 2014 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN25801 Rev. 1.0.2 2 Q1