Dual-4 A, High-Speed, Low-Side Gate Drivers FAN3213, FAN3214 Description The FAN3213 and FAN3214 dual 4 A gate drivers are designed to drive N channel enhancement mode MOSFETs in low side www.onsemi.com switching applications by providing high peak current pulses during the short switching intervals. They are both available with TTL input thresholds. Internal circuitry provides an undervoltage lockout 8 function by holding the output LOW until the supply voltage is within the operating range. In addition, the drivers feature matched internal 1 propagation delays between A and B channels for applications SOIC8 requiring dual gate drives with critical timing, such as synchronous CASE 751EB rectifiers. This also enables connecting two drivers in parallel to effectively double the current capability driving a single MOSFET. MARKING DIAGRAM The FAN3213/14 drivers incorporate MillerDrive architecture for the final output stage. This bipolarMOSFET combination provides 8 high current during the Miller plateau stage of the MOSFET turnon/turnoff process to minimize switching loss, while providing 321xT railtorail voltage swing and reverse current capability. ALYW The FAN3213 offers two inverting drivers and the FAN3214 offers two noninverting drivers. Both are offered in a standard 8pin SOIC 1 package. A = Assembly Location Features L = Wafer Lot YW = Assembly Start Week IndustryStandard Pin Out = PbFree Package 4.5 to 18 V Operating Range (Note: Microdot may be in either location) 5 A Peak Sink/Source at V = 12 V DD 4.3 A Sink/2.8 A Source at V = 6 V OUT ORDERING INFORMATION TTL Input Thresholds See detailed ordering and shipping information on page 15 of this data sheet. Two Versions of Dual Independent Drivers: Dual Inverting (FAN3213) Dual NonInverting (FAN3214) Internal Resistors Turn Driver Off if No Inputs Miller Drive Technology 12 ns/9 ns Typical Rise/Fall Times with 2.2 nF Load Typical Propagation Delay Under 20 ns Matched within 1 ns to the Other Channel Double Current Capability by Paralleling Channels Standard SOIC8 Package Rated from 40C to +125C Ambient These are PbFree Devices Applications SwitchMode Power Supplies HighEfficiency MOSFET Switching Synchronous Rectifier Circuits DCtoDC Converters Motor Control Semiconductor Components Industries, LLC, 2008 1 Publication Order Number: April, 2020 Rev. 3 FAN3214/DFAN3213, FAN3214 PIN CONFIGURATIONS NC 1 8 NC NC 1 8 NC INA 2 A 7 OUTA INA 2 A 7 OUTA GND 3 6 VDD GND 3 6 VDD INB 4 5 OUTB INB 4 5 OUTB B B FAN3213 FAN3214 Figure 1. Pin Configurations PACKAGE OUTLINES 1 8 2 7 3 6 4 5 Figure 2. SOIC 8 (Top View) THERMAL CHARACTERISTICS (Note 1) JL JT JA JB JT (Note 2) (Note 3) (Note 4) (Note 5) (Note 6) Package Unit 8Pin Small Outline Integrated Circuit (SOIC) 38 29 87 41 2.3 C/W 1. Estimates derived from thermal simulation actual values depend on the application. 2. Theta JL ( ): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any thermal pad) JL that are typically soldered to a PCB. 3. Theta JT ( ): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is held at a uniform JT temperature by a top side heatsink. 4. Theta JA ( ): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow. The value given JA is for natural convection with no heatsink using a 2S2P board, as specified in JEDEC standards JESD512, JESD515, and JESD517, as appropriate. 5. Psi JB ( ): Thermal characterization parameter providing correlation between semiconductor junction temperature and an application JB circuit board reference point for the thermal environment defined in Note 4. For the MLP8 package, the board reference is defined as the PCB copper connected to the thermal pad and protruding from either end of the package. For the SOIC8 package, the board reference is defined as the PCB copper adjacent to pin 6. 6. Psi JT ( ): Thermal characterization parameter providing correlation between the semiconductor junction temperature and the center of JT the top of the package for the thermal environment defined in Note 4. www.onsemi.com 2