Gate Drivers, High-Speed, Low-Side, Dual 4-A FAN3223/FAN3224/FAN3225 Description The FAN322325 family of dual 4 A gate drivers is designed to drive N channel enhancement mode MOSFETs in low-side www.onsemi.com switching applications by providing high peak current pulses during the short switching intervals. The driver is available with either TTL or CMOS input thresholds. Internal circuitry provides an undervoltage lockout function by holding the output LOW until the SOIC8 8 supply voltage is within the operating range. In addition, the drivers CASE 751EB 1 feature matched internal propagation delays between A and B channels for applications requiring dual gate drives with critical 8 SOIC8 EP timing, such as synchronous rectifiers. This also enables connecting CASE 751AC 1 two drivers in parallel to effectively double the current capability driving a single MOSFET. MARKING DIAGRAMS The FAN322X drivers incorporate MillerDrive architecture for the final output stage. This bipolarMOSFET combination provides 8 8 high current during the Miller plateau stage of the MOSFET turnon / Y&Z&2&K XXXXX turn off process to minimize switching loss, while providing FAN AYWW railtorail voltage swing and reverse current capability. XXXXX The FAN3223 offers two inverting drivers and the FAN3224 offers 1 1 two noninverting drivers. Each device has dual independent enable SOIC8 EP SOIC8 pins that default to ON if not connected. In the FAN3225, each channel has dual inputs of opposite polarity, which allows configuration as XXX = Specific Device Code noninverting or inverting with an optional enable function using the A = Assembly Lot Code second input. If one or both inputs are left unconnected, internal Y = Year resistors bias the inputs such that the output is pulled LOW to hold the WW = Work Week = PbFree Package power MOSFET OFF. Y = ON Semiconductor Logo Graphic Features &Z = Assembly Plant Code IndustryStandard Pinouts &2 = 2Digit Date Code (Year and Week) 4.5 V to 18 V Operating Range &K = 2Digit Lot Run Traceability Code 5 A Peak Sink/Source at V = 12 V (Note: Microdot may be in either location) DD 4.3 A Sink / 2.8 A Source at V = 6 V OUT ORDERING INFORMATION Choice of TTL or CMOS Input Thresholds See detailed ordering and shipping information on page 21 of Three Versions of Dual Independent Drivers: this data sheet. Dual Inverting + Enable (FAN3223) Applications Dual NonInverting + Enable (FAN3224) DualInputs (FAN3225) SwitchMode Power Supplies Internal Resistors Turn Driver Off If No Inputs High-Efficiency MOSFET Switching MillerDrive Technology Synchronous Rectifier Circuits 12 ns / 9 ns Typical Rise/Fall Times (2.2 nF Load) DC-to-DC Converters Under 20 ns Typical Propagation Delay Matched within 1 ns to the Motor Control Other Channel Automotive-Qualified Systems Double Current Capability by Paralleling Channels Related Resources 8Lead SOIC and 8Lead SOIC Exposed Pad Package AN6069 Application Review and Rated from 40C to +125C Ambient Comparative Evaluation of LowSide Gate Drivers Automotive Qualified to AEC-Q100 These are PbFree Devices Semiconductor Components Industries, LLC, 2020 1 Publication Order Number: April, 2020 Rev. 1 FAN3223F085/DFAN3223/FAN3224/FAN3225 PACKAGE OUTLINES 1 8 1 8 2 7 2 7 3 6 3 6 4 5 4 5 Figure 1. SOIC 8 (Top View) Figure 2. SOIC8EP (Top View) THERMAL CHARACTERISTICS (Note 1) L JT JA JB JT (Note 2) (Note 3) (Note 4) (Note 5) (Note 6) Package Unit 8Pin Small Outline Integrated Circuit (SOIC) 38 29 87 41 2.3 C/W 8Pin Small Outline Integrated Circuit with Exposed Pad 5.1 75 40 5.1 7 C/W (SOICEP) 1. Estimates derived from thermal simulation actual values depend on the application. 2. Theta JL ( ): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any thermal pad) JL that are typically soldered to a PCB. 3. Theta JT ( ): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is held at a uniform JT temperature by a top side heatsink. 4. Theta JA ( ): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow. The value given JA is for natural convection with no heatsink using a 2S2P board, as specified in JEDEC standards JESD512, JESD515, and JESD517, as appropriate. 5. Psi JB ( ): Thermal characterization parameter providing correlation between semiconductor junction temperature and an application JB circuit board reference point for the thermal environment defined in Note 4. For the SOIC8EP package, the board reference is defined as the PCB copper connected to the thermal pad and protruding from either end of the package. For the SOIC8 package, the board reference is defined as the PCB copper adjacent to pin 6. 6. Psi JT ( ): Thermal characterization parameter providing correlation between the semiconductor junction temperature and the center of JT the top of the package for the thermal environment defined in Note 4. www.onsemi.com 2