Dual 2-A High-Speed, Low-Side Gate Drivers FAN3226, FAN3227, FAN3228, FAN3229 Description www.onsemi.com The FAN322629 family of dual 2 A gate drivers is designed to drive N channel enhancement mode MOSFETs in low side switching applications by providing high peak current pulses during 8 the short switching intervals. The driver is available with either TTL 1 or CMOS input thresholds. Internal circuitry provides an SOIC8 undervoltage lockout function by holding the output low until the CASE 751EB supply voltage is within the operating range. In addition, the drivers feature matched internal propagation delays between A and B MARKING DIAGRAM channels for applications requiring dual gate drives with critical timing, such as synchronous rectifiers. This enables connecting two drivers in parallel to effectively double the current capability driving 8 a single MOSFET. Y&Z&2&K The FAN322X drivers incorporate MillerDrive architecture for FAN the final output stage. This bipolarMOSFET combination provides XXXXX high current during the Miller plateau stage of the MOSFET turnon/ 1 turn off process to minimize switching loss, while providing railtorail voltage swing and reverse current capability. The FAN3226 offers two inverting drivers and the FAN3227 offers Y = ON Semiconductor Logo Graphic &Z = Assembly Plant Code two noninverting drivers. Each device has dual independent enable &2 = 2Digit Data Code (Year & Week) pins that default to ON if not connected. In the FAN3228 and &K = 2Digit Lot Run Traceability Code FAN3229, each channel has dual inputs of opposite polarity, which (Note: Microdot may be in either location) allows configuration as noninverting or inverting with an optional enable function using the second input. If one or both inputs are left unconnected, internal resistors bias the inputs such that the output is ORDERING INFORMATION pulled low to hold the power MOSFET off. See detailed ordering and shipping information on page 20 of this data sheet. Features IndustryStandard Pinouts Features (Continued) 4.5V to 18V Operating Range 8Lead SOIC Package 3A Peak Sink/Source at V = 12 V DD Rated from 40C to +125C Ambient 2.4 ASink/1.6A Source at V = 6 V OUT AECQ100 Qualified and PPAP Capable Choice of TTL or CMOS Input Thresholds These are PbFree Devices Four Versions of Dual Independent Drivers: Dual Inverting + Enable (FAN3226) Applications Dual NonInverting + Enable (FAN3227) SwitchMode Power Supplies Dual Inputs in Two PinOut Configurations: HighEfficiency MOSFET Switching Compatible with FAN3225x (FAN3228) Synchronous Rectifier Circuits Compatible with TPS2814D (FAN3229) Internal Resistors Turn Driver Off If No Inputs DCtoDC Converters MillerDrive Technology Motor Control 12ns/9ns Typical Rise/Fall Times (1nF Load) Servers Under 20ns Typical Propagation Delay Matched within 1 ns to AutomotiveQualified Systems the Other Channel Double Current Capability by Paralleling Channels Semiconductor Components Industries, LLC, 2019 1 Publication Order Number: November, 2020 Rev. 4 FAN3229TF085/DFAN3226, FAN3227, FAN3228, FAN3229 PIN CONFIGURATIONS 1 8 1 8 INA 1 8 1 8 ENA ENB ENA ENB INA+ INA+ GND + + INA 2 A 7 OUTA INA 2 A 7 OUTA INB+ 2 A 7 OUTA INA 2 A 7 OUTA GND 3 6 VDD GND 3 6 VDD GND 3 6 VDD INB+ 3 6 VDD + + INB 4 B 5 OUTB INB 4 B 5 OUTB INB 4 B 5 OUTB INB 4 B 5 OUTB FAN3226 FAN3227 FAN3228 FAN3229 Figure 1. Pin Configurations PACKAGE OUTLINES 1 8 2 7 3 6 4 5 Figure 2. SOIC 8 (Top View) THERMAL CHARACTERISTICS (Note 1) JL JT JA JB JT (Note 2) (Note 3) (Note 4) (Note 5) (Note 6) Package Unit 8Pin Small Outline Integrated Circuit (SOIC) 40 31 89 43 3.0 C/W 1. Estimates derived from thermal simulation actual values depend on the application. 2. Theta JL ( ): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any thermal pad) JL that are typically soldered to a PCB. 3. Theta JT ( ): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is held at a uniform JT temperature by a top side heatsink. 4. Theta JA ( ): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow. The value given JA is for natural convection with no heatsink using a 2S2P board, as specified in JEDEC standards JESD512, JESD515, and JESD517, as appropriate. 5. Psi JB ( ): Thermal characterization parameter providing correlation between semiconductor junction temperature and an application JB circuit board reference point for the thermal environment defined in Note 4. For the SOIC8 package, the board reference is defined as the PCB copper adjacent to pin 6. 6. Psi JT ( ): Thermal characterization parameter providing correlation between the semiconductor junction temperature and the center of JT the top of the package for the thermal environment defined in Note 4. www.onsemi.com 2