Highly Integrated Quasi-Resonant Current Mode PWM Controller FAN6300A / FAN6300H The highly integrated FAN6300A/H of PWM controller provides www.onsemi.com several features to enhance the performance of flyback converters. FAN6300A is applied on quasiresonant flyback converters where maximum operating frequency is below 100kHz. FAN6300H is suitable for highfrequency operation (up to 190 kHz). A builtin HV startup circuit can provide more startup current to reduce the startup time of the controller. Once the V voltage exceeds the turnon DD SOIC8 threshold voltage, the HV startup function is disabled immediately to CASE 751EB reduce power consumption. An internal valley voltage detector ensures power system operates at quasiresonant operation over MARKING DIAGRAM a widerange of line voltage and any load conditions, as well as reducing switching loss to minimize switching voltage on drain of power MOSFET. 6300x = Specific Device Code To minimize standby power consumption and lightload efficiency, (x = A or H) 6300x ALYWX A = Assembly Location a proprietary greenmode function provides offtime modulation to L = Wafer Lot Traceability decrease switching frequency and perform extended valley voltage YW = Date Code switching to keep to a minimum switching voltage. The operating X = Manufacture Flow frequency is limited by minimum t time, which is 38 s to 8 s in OFF = Pb Free FAN6300A and 13 s to 3 s in FAN6300H, so FAN6300H can operate at higher switching frequency than FAN6300A. PIN ASSIGNMENT FAN6300A/H controller also provides many protection functions. Pulsebypulse current limiting ensures the fixedpeak current limit DET 1 8 HV level, even when a short circuit occurs. Once an opencircuit failure occurs in the feedback loop, the internal protection circuit disables PWM output immediately. As long as VDD drops below the turnoff FB 2 7 NC threshold voltage, the controller also disables PWM output. The gate FAN6300H output is clamped at 18 V to protect the power MOS from high CS 3 6 VDD gate source voltage conditions. The minimum t time limit OFF prevents the system frequency from being too high. If the DET pin GND 4 5 GATE triggers OVP, internal OTP is triggered and the power system enters latchmode until AC power is removed. (Top View) The FAN6300A/H controller is available in the 8pin SOIC8 package. ORDERING INFORMATION See detailed ordering and shipping information on page 11 of Features this data sheet. HighVoltage Startup QuasiResonant Operation CyclebyCycle Current Limiting VDD Pin and Output Voltage (DET Pin) OVP Latched PeakCurrentMode Control Low Frequency Operation (below 100 kHz) LeadingEdge Blanking (LEB) for FAN6300A Internal Minimum t OFF High Frequency Operation (up to 190 kHz) Internal 5 ms SoftStart for FAN6300H Over Power Compensation GATE Output Maximum Voltage Applications AutoRecovery OverCurrent Protection (FB Pin) AC/DC NB Adapters AutoRecovery OpenLoop Protection (FB Pin) OpenFrame SMPS Semiconductor Components Industries, LLC, 2021 1 Publication Order Number: June, 2021 Rev. 1 FAN6300H/DFAN6300A / FAN6300H APPLICATION DIAGRAM Figure 1. Typical Application INTERNAL BLOCK DIAGRAM HV VDD 8 6 Internal Bias OVP I H V Two Steps 4 .2V UVLO 27 V 16 V/ 10 V/ 8 V 2 R Latched Soft-Start 2 FB 5 ms FBOLP Timer 52 ms R 2 .1 ms 30 s Starter DRV Blanking Circuit SE T S Q 5 3 GATE CS PWM 18 V Over-Power Current Limit R C L R Q Compensation I D ET Latched 0.3 V Valley t OFF-MIN Detector V D ET t TIME-OUT V D ET t OFF S/H Latched Blanking 2. 5V DETOVP DET 1 Internal 0 .3 V Latched OTP I D ET 5V 4 7 NC GND Figure 2. Functional Block Diagram www.onsemi.com 2