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It is designed to provide an optimal Max r = 8.5m at V = 10V, I = 12A DS(on) GS D Synchronous Buck power stage in terms of efficiency and PCB Max r = 12.4m at V = 4.5V, I = 10A DS(on) GS D utilization. The low switching lossHigh Sid MOSFET is com- Q2: N-Channel plemented by a Low Conduction LossLow Sid SyncFET. Max r = 5.5m at V = 10V, I = 16A DS(on) GS D Applications Max r = 7.0m at V = 4.5V, I = 14A DS(on) GS D Synchronous Buck Converter for: Low Qg high side MOSFET Notebook System Power Low r low side MOSFET DS(on) Thermally efficient dual Power 56 package General Purpose Point of Load Pinout optimized for simple PCB design RoHS Compliant G1G1 D1D1 Q2 D1D1 5 4 D1D1 D1D1 6 3 S1S1//DD22 G2G2 7 2 S2S2 S2S2 8 1 Q1 S2S2 Power 56 MOSFET Maximum Ratings T = 25C unless otherwise noted A Symbol Parameter Q1 Q2 Units V Drain to Source Voltage 30 30 V DS V Gate to Source Voltage 20 20 V GS Drain Current -Continuous T = 25C 32 30 C -Continuous T = 25C (Note 1a) 12 16 I A A D -Pulsed 60 60 Power Dissipation for Single Operation (Note 1a) 2.5 P W D (Note 1b) 1.0 T , T Operating and Storage Junction Temperature Range -55 to +150 C J STG Thermal Characteristics R Thermal Resistance, Junction to Ambient (Note 1a) 50 JA R Thermal Resistance, Junction to Ambient (Note 1b) 120 C/W JA R Thermal Resistance, Junction to Case 3 1.2 JC Package Marking and Ordering Information Device Marking Device Package Reel Size Tape Width Quantity FDMS9600S FDMS9600S Power 56 13 12mm 3000 units 1 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMS9600S Rev.D2