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Based on the TRUESENSE 5.5 micron Interline Transfer CCD Platform, the sensor features broad dynamic range, www.onsemi.com excellent imaging performance, and a flexible readout architecture that enables use of 1, 2, or 4 outputs for full resolution readout up to 4 frames per second. A vertical overflow drain structure suppresses image blooming and enables electronic shuttering for precise exposure control. The sensor is available with the TRUESENSE Sparse Color Filter Pattern, which provides a 2x improvement in light sensitivity compared to a standard color Bayer part. The sensor shares common PGA pin out and electrical configurations with other devices based on the TRUESENSE 5.5 micron Interline Transfer CCD Platform, allowing a single camera design to be leveraged to support multiple members of this sensor family. Figure 1. KAI29050 CCD Image Sensor Table 1. GENERAL SPECIFICATIONS Parameter Typical Value Architecture Interline CCD Progressive Scan Features Total Number of Pixels 6644 (H) x 4452 (V) Bayer Color Pattern, TRUESENSE Sparse Number of Effective Pixels 6600 (H) x 4408 (V) Color Filter Pattern, and Monochrome Number of Active Pixels 6576 (H) x 4384 (V) Pixel Size 5.5 m (H) x 5.5 m (V) Configurations Active Image Size 36.17 mm (H) x 24.11 mm (V) Progressive Scan Readout 43.47 mm (diag.), 35 mm Optical Format Flexible Readout Architecture Aspect Ratio 3:2 High Frame Rate Number of Outputs 1, 2, or 4 High Sensitivity Charge Capacity 20,000 electrons Output Sensitivity 34 V/e Low Noise Architecture Quantum Efficiency Excellent Smear Performance Pan (AXA, QXA) 43% R, G, B (FXA, QXA) 28%, 35%, 38% Package Pin Reserved for Device Read Noise (f = 40 MHz) 12 electrons rms Identification Dark Current Photodiode 7 electrons/s VCCD 140 electrons/s Applications Dark Current Doubling Temp. Industrial Imaging and Inspection Photodiode 7C VCCD 9C Medical Imaging Dynamic Range 64 dB Security Charge Transfer Efficiency 0.999999 Blooming Suppression > 300 X Smear Estimated 100 dB ORDERING INFORMATION Image Lag < 10 electrons See detailed ordering and shipping information on page 2 of this data sheet. Maximum Pixel Clock Speed 40 MHz Maximum Frame Rates Quad Output 4 fps Dual Output 2 fps Single Output 1 fps Package 72 pin PGA Cover Glass AR coated, 2 Sides NOTE: All parameters are specified at T = 40C unless otherwise noted. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: July, 2018 Rev. 10 KAI29050/D