TENTATIVE SPECIFICATIONS DATE Aug.27 2013 PRODUCT NAME: LC706200CM 1. Case Outline: Wafer Ring(8inch) 2. Function: Semiconductor IC for Digital Silicon Microphone includes Pre-amplifier and Sigma Delta Modulator and Charge Pump. 3. Application: Cellular phone and other 4. Absolute Maximum Ratings at Ta=25C, GND = 0V Parameter Symbol Pin Name Min Max Units Maximum power supply voltage V max -0.3 +4.0 V DD VDD V max -0.3 VDD+0.3 V CLK,CLKSEL CLK Maximum input voltage V max -0.3 VDD+0.3 V IN IN Maximum output voltage Vomax -0.3 VDD+0.3 V DATA Operating temperature range Ta -30 70 Storage temperature range Tstg -40 85 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Pad Coordinate (0 ,0) PAD Size (88,-88)VDD SUB(822,-88) (88,-371)CLKSEL 80m (Jacket Open Area) IN(774,-557) (88,-687)CLK 80m GUARD(805,-811) (88,-890)GND VB(799,-1102) (88,-1098)DATA 5. Circuit Parameters Parameter Symbol Pin Name Test Condition Min Typ Max Units 0.4 pF Input capacitance of die Cin IN Note: IN-Pin has a limited protection against ESD. Value of IN-Pin is proven by design. 6. DC Electrical Characteristics Ratings at Ta=25C,VDD=3.3V,GND=0V,Fclk=2.4MHz, Fduty =50% Parameter Symbol Pin Name Condition Min Typ Max Units 1.64 3.3 3.6 V Power supply voltage VDD VDD Power consumption VDD=3.3V 800 uA (IO Power consumption IDD VDD is not Included) VDD=3.3V 200 nA Standby Current ISTBY VDD DATAIol=0.5mA CLK, DATA V Input/Output LOW level Viol 0.35VDD CLKSEL DATAIoh=-0.5mA CLK, DATA V Input/Output HIGH level Vioh 0.65VDD CLKSEL ( - ) 20130522 TWJ/MH/EX No. 1 LC706200CM V VDD=3.3V 10.5 Charge pump voltage Vbias VB/SUB Parameter Symbol Pin Name Condition Min Typ Max Units Charge Pump voltage % -8 +8 Tolerance VB/SUB tolerance 7. AC Electrical Characteristics Ratings at Ta=+25,VDD=3.3V,GND=0V, Signal Frequency=1KHz, Measurement frequency=100Hz20KHz, Fclk=2.4MHz,Fduty =50%, Bypass capacitor=0.1uF(VDD-GND) Parameter Symbol Pin Name Condition Min Typ Max Units Clock Frequency 1 2.4 3.25 MHz Fclk CLK ( Normal Operation ) Clock Frequency 1 KHz Fclk SL CLK ( Sleep Mode ) 60 % 40 Clock Duty Fduty CLK 50 Over Sampling Ratio OSR 0dBFS Maximum Input Voltage ( = 120dBSPL ) 158.5 mVrms (Input Full Scale Vin IN Voltage) Vout=0dBFS % ( = 120dBSPL) 10 THD 0 DATA ( = 158.5mVrms) (THD) Vout=-5dBFS ( = 115dBSPL) % THD+N 1 5 DATA THD / THD+N ( = 89.1mVrms) 1 (THD+N) 1KHz Sin-Wave Vout=-20dBFS ( = 100dBSPL) % THD+N 2 1 DATA ( = 15.8mVrms) 1 (THD+N) 50-4KHz Sin-Wave Bandwidth 20KHz -87 dBFS Digital Noise Floor DNF1 DATA A-weighted 217Hz Square, PSRR 1 10MHz-Broadband -70 dBFS PSRR DATA Noise, 100mVpp Transfer function 2 18 dB TF1 DATA Wake Up Time 1 Fclk=2.4MHz 10 ms WUT CLK Fclk=1KHz 10 ms Fall Asleep Time 1 FAT Note1 : 1 are Reference data:No measurement. Note22 Each product has been designed with performance of +/-0.5dB tolerance for transfer function however it s not checked in outgoing inspection. Note3: Input Full Scale Voltage 0dBFS is equivalent to 120dBSPL (= 158.5mVrms). Note4: SNR Input Level Condition is 26dBFS (= 7.9mVrms, 94dBSPL, 1Pa). ( - ) No. 2