LC717A00AR CapacitanceDigitalConverter LSI for Electrostatic Capacitive Touch Sensors Overview www.onsemi.com The LC717A00AR is a high-performance, low-cost capacitance- digital-converter LSI for electrostatic capacitive touch sensor, especially focused on usability. It has 8 channels capacitance-sensor input. The built-in logic circuit can detect the state (ON/OFF) of each input and output the result. This makes it ideal for various switch applications. The calibration function is automatically performed by the built-in VCT28 logic circuit during power activation or whenever there are CASE 601AE environmental changes. In addition, since initial settings of parameters, such as gain, are configured, LC717A00AR can operate MARKING DIAGRAM as stand-alone when the recommended switch pattern is applied. Also, since LC717A00AR has a serial interface compatible with 2 I C and SPI bus, parameters can be adjusted using external devices XXXXXXXX whenever necessary. Moreover, outputs of the 8-input capacitance YMDDD data can be detected and measured as 8-bit data. Features XXXXX = Specific Device Code Detection System: Differential Capacitance Detection Y = Year (Mutual Capacitance Type) M = Month Input Capacitance Resolution: Can Detect Capacitance Changes in DDD = Additional Traceability Data the Femto Farad Order Measurement Interval (8 Differential Inputs): ORDERING INFORMATION 18 ms (Typ) (at Initial Configuration) See detailed ordering and shipping information on page 11 of this data sheet. 3 ms (Typ) (at Minimum Interval Configuration) External Components for Measurement: Not Required Current Consumption: 320 A (Typ) (V = 2.8 V) DD 740 A (Typ) (V = 5.5 V) DD Supply Voltage: 2.6 V to 5.5 V Detection Operations: Switch Packages: VCT28 2 Interface: I C Compatible Bus or SPI Selectable Semiconductor Components Industries, LLC, 2013 1 Publication Order Number: October, 2017 Rev. 3 LC717A00AR/DLC717A00AR Specifications Table 1. ABSOLUTE MAXIMUM RATINGS (T = 25C, V = 0 V) A SS Parameter Symbol Ratings Unit Remarks Supply Voltage V 0.3 to +6.5 V DD Input Voltage V 0.3 to V + 0.3 V (Note 1) IN DD Output Voltage V 0.3 to V + 0.3 V (Note 2) OUT DD Power Dissipation P 160 mW T = +105 C, Mounted on a substrate (Note 3) d max A Peak Output Current I 8 mA Per terminal, 50% Duty ratio (Note 2) OP Total Output Current I 40 mA Output total value of LSI, 25% Duty ratio OA Storage Temperature T 55 to +125 C stg Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Apply to Cin0 to 7, Cref, nRST, SCL, SDA, SA, SCK, SI, nCS, GAIN. 2. Apply to Cdrv, Pout0 to 7, SDA, SO, ERROR, INTOUT. 3. 4-layer glass epoxy board (40 50 0.8t mm). Table 2. RECOMMENDED OPERATING CONDITIONS Parameter Symbol Conditions Min Typ Max Unit Remarks Operating Supply Voltage V 2.6 5.5 V DD Supply Ripple + Noise V 20 mV (Note 4) PP Operating Temperature T 40 25 105 C opr Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 4. Inserting a high-valued capacitor and a low-valued capacitor in parallel between V and V is recommended. In this case, the small-valued DD SS capacitor should be at least 0.1 F, and is mounted near the LSI. Table 3. ELECTRICAL CHARACTERISTICS (V = 0 V, V = 2.6 to 5.5 V, T = 40 to +105C, Unless otherwise specified, the Cdrv drive frequency is f = 143 kHz. SS DD A CDRV Not tested at low temperature before shipment.) Parameter Symbol Conditions Min Typ Max Unit Remarks Capacitance Detection Resolution N 8 bit Output Noise RMS N Minimum gain setting 1.0 LSB (Notes 5, 7) RMS Input Offset Capacitance Coff 8.0 pF (Notes 5, 7) RANGE Adjustment Range Input Offset Capacitance Coff 8 bit RESO Adjustment Resolution Cin Offset Drift Cin Minimum gain setting 8 LSB (Note 5) DRIFT Cin Detection Sensitivity Cin Minimum gain setting 0.04 0.12 LSB/fF (Note 6) SENSE Cin Pin Leak Current I Cin = HiZ 25 500 nA Cin Cin Allowable Parasitic Input Cin Cin against V 30 pF (Notes 5, 7) SUB SS Capacitance Cdrv Drive Frequency f 100 143 186 kHz CDRV Cdrv Pin Leak Current I Cdrv = HiZ 25 500 nA CDRV nRST Minimum Pulse Width t 1 s NRST Power-on Reset Time t 20 ms POR Power-on Reset Operation t 10 ms (Note 5) POROP Condition: Hold Time Power-on Reset Operation V 0.1 V (Note 5) POROP Condition: Input Voltage www.onsemi.com 2