LC75886PW 1/4, 1/3-Duty LCD Driver with Key Input Function Overview The LC75886PW is 1/4 duty and 1/3 duty LCD display driver that can www.onsemi.com directly drive up to 224 segments and can control up to 5 general- purpose output ports. This product also incorporates a key scan circuit that accepts input from up to 30 keys to reduce printed circuit board wiring. Features Key input function for up to 30 keys (A key scan is performed only when a key is pressed.) 1/4 duty 1/3 bias and 1/3 duty 1/3 bias drive schemes can be controlled from serial data. SQFP80 12x12 / SQFP80 Capable of driving up to 224 segments using 1/4 duty and up to 171 segments using 1/3 duty. Switching between key scan output and segment output can be controlled from serial data. The key scan operation enabled/disabled state can be controlled from serial data. Switching between segment output port and general-purpose output port can be controlled from serial data. Switching between general-purpose output port, clock output port, and segment output port can be controlled from serial data. (Up to 5 general-purpose output ports and up to one clock output port) Serial data I/O supports CCB* format communication with the system controller. (Support 3.3 V and 5 V operation) Sleep mode and all segments off functions that are controlled from serial data. The frame frequency of the common and segment output waveforms can be controlled from serial data. Switching between RC oscillator operating mode and external clock operationg mode can be controlled from serial data. Direct display of display data without the use of a decoder provides high generality. Provision of an on-chip voltage-detection type reset circuit prevents incorrect displays. pin provided for forcibly initializing the IC internal circuits. RES * Computer Control Bus (CCB) is an ON Semiconductors original bus format and the bus addresses are controlled by ON Semiconductor. ORDERING INFORMATION See detailed ordering and shipping information on page 36 of this data sheet. Semiconductor Components Industries, LLC, 2017 1 Publication Order Number : July 2017 - Rev. 1 LC75886PW/D LC75886PW Specifications Absolute Maximum Ratings at Ta = 25 C, V = 0 V SS Parameter Symbol Conditions Ratings Unit V max V 0.3 to +7.0 Maximum supply voltage V DD DD Input voltage V 1 0.3 to +7.0 IN CE, CL, DI, RES V V 2 OSC, TEST, V 1, V 2, KI1 to KI5 0.3 to V +0.3 IN DD DD DD Output voltage V 1 DO 0.3 to +7.0 OUT 0.3 to V +0.3 V OSC, S1 to S57, COM1 to COM4, KS1 to KS6, DD V 2 OUT P1 to P5 Output current I 1 300 S1 to S57 A OUT I 2 3 COM1 to COM4 OUT I 3 1 KS1 to KS6 mA OUT I 4 5 P1 to P5 OUT Allowable power dissipation Pd max 200 mW Ta = 85C 40 to +85 Operating temperature Topr C Storage temperature Tstg 55 to +125 C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Allowable Operating Ranges at Ta = 40 to +85C, V = 0 V SS Ratings Parameter Symbol Conditions Unit min typ max Supply voltage V V 4.5 6.0 V DD DD Input voltage V1 V 1 2/3V V DD DD DD DD V V2 V 2 1/3V V DD DD DD DD Input high level voltage V 1 RES 0.4V 6.0 IH CE, CL, DI, DD V 2 KI1 to KI5 0.6V V V IH DD DD V 3 OSC: External clock operating mode 0.4V V IH DD DD Input low level voltage V 1 CE, CL, DI, RES 0 0.2V IL DD V 2 KI1 to KI5 0 0.2V V IL DD V 3 OSC: External clock operating mode 0 0.2V IL DD Recommended external R OSC: RC oscillation operating mode OSC 39 k resistor for RC oscillation Recommended external C OSC: RC oscillation operating mode OSC 1000 pF capacitor for RC oscillation Guaranteed range of RC f OSC: RC oscillation operating mode OSC 19 38 76 kHz oscillation External clock operating f OSC: External clock operating mode CK 10 38 76 kHz frequency Figure4 External clock duty cycle D OSC: External clock operating mode CK 30 50 70 % Figure4 Data setup time t CL, DI Figure2 , Figure3 160 ns ds Data hold time t CL, DI Figure2 , Figure3 160 ns dh CE wait time t CE, CL Figure2 , Figure3 160 ns cp CE setup time t CE, CL Figure2 , Figure3 160 ns cs CE hold time t CE, CL Figure2 , Figure3 160 ns ch High level clock pulse width t CL Figure2 , Figure3 160 ns H Low level clock pulse width t CL Figure2 , Figure3 160 ns L Rise time t CE, CL, DI Figure2 , Figure3 160 ns r Fall time t CE, CL, DI Figure2 , Figure3 160 ns f DO output deley time t DO R = 4.7 k C = 10 pF *1 dc PU L 1.5 s Figure2 , Figure3 DO rise time t DO R = 4.7 k C = 10 pF *1 dr PU L 1.5 s Figure2 , Figure3 Note: *1 Since the DO pin is an open-drain output, these times depend on the values of the pull-up resistor R and the load capacitance C . PU L Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. www.onsemi.com 2