LC823450 Low Power & High-Resolution Audio Processing System LSI for Portable Sound Solution www.onsemi.com Description LC823450 is an ultralow power, 32bit, 192 kHz highresolution audiocapable signal processing systemonchip (SoC). It consists of dual ARM CortexM3, 32bit DSP (LPDSP32) core, hard wired MP3 encoder/decoder, and integrated SRAM. It is also equipped with analog peripheral functionality, such as PLLs, classD stereo HP TQFP128 14 x 14/ TQFP128L amplifier, 6band equalizer and ADCs/DACs. Our proprietary CASE 932BA LPDSP32 supports Noise/Echo cancellation, and playback speed control capability for MP3, WMA, AAC and PCM with VBR. With finetuned power management and dedicated hard wired audio blocks, LC823450 provides a significantly longer battery life without compromising audio quality, for voice recorders and wearable audio WLCSP154 5.52 x 5.33 applications. CASE 567LD This document describes features, basic functions, electrical specifications, characteristics, application diagram and package dimension of this LSI. Features Ultra Low Power Consumption LFBGA240 11 x 11 CASE 566EY Arm Cortex M3 Dual Core Proprietary 32bit DSP Core (LPDSP32) ORDERING INFORMATION Internal Large Scale Size SRAM: 1656 kB (1.5 MB + 120 kB) See detailed ordering and shipping information on page 53 of HighResolution 32bit & 192 kHz Audio Processing Capability this data sheet. Several DSP Codes Available for Audio Functions Hard Wired Audio Functions Builtin MP3 Decoder, MP3 Encoder 6 Band Equalizer Synchronous SRC, Asynchronous SRC, etc. Analog Blocks Builtin System PLL, Audio PLL 16bit DAC, ClassD amp, etc. USB2.0 Device and USB2.0 Host with a Integrated PHY eMMC and SD card I/F Serial Flash I/F(Quad) with Cache Memory 2 SPI, UART, I C, etc. Typical Applications Sound Recorders Wearable Audio Players Bluetooth Headsets Smart Phone Accessories Semiconductor Components Industries, LLC, 2017 1 Publication Order Number: March, 2020 Rev. 10 LC823450/DLC823450 ABSTRACT Features Real Time Clock CortexM3 Dual Core, AMBA (AHB/APB) System 2 modes below are available Internal SRAM (1.5M-byte) General RTC mode: RTC w/o key input Internal ROM (256k-byte). Boot code, Standard KeyInt RTC mode: RTC w/ key input which Functions enables power on function SDRAM Controller (1 * CS) SWD (Serial Wire Debug) is supported as the debug 64M to 256Mbit SDRAM / Mobile SDRAM interface. External Memory Controller (2 * CS) SWV (Serial Wire Viewer) is supported as the trace NOR FLASH, SRAM, ROM supported, 8/16 bit I/F interfaceOnly one of CortexM3 Dual Core can be LCD controller supported traced. Internal ROM boot and External memory device boot available Availability of features explained here depends on products. DMA Controller (8ch) 1 MP3 Hard Wired Encoder/Decoder Interrupt Controller (External 90ch, Internal 82ch) MP3 MPEG1, MPEG2, MPEG2.5 SPI (1ch) Sampling rate: 8 kHz,11.025 kHz,12 kHz,16 kHz, Serial Flash I/F (1ch) 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz Quad SPI, cache memory (16k-byte, 4way set Bit rate:8 Kbps to 320 Kbps (DecoderVBR associative, 128line) function available supported) 1.8V dedicated power supply LPDSP32 System UART (3ch) Internal SRAM (120 kbyte) UART1: w/flow control (CTS, RTS) Internal ROM (220 kbyte) UART0, UART2: w/o flow control 2 2 WMA (Microsoft WMA Decoder Profile Level3) I C (2ch) Single Master, Full/Standard Sampling rate: 8 kHz, 11.025 kHz, 16 kHz, GPIO (90ch) 22.05 kHz, 32 kHz, 44.1 kHz, 48 kHz Plain Timer w/ Watch Dog Timer (1ch3) Bit rate: 5 Kbps to 320 Kbps (VBR supported) Multiple Timer (2ch4) AAC (MPEG4 LCAAC) 10bit ADC (6ch) Bit rate: 8 Kbps to 320 Kbps (VBR supported) SD Card I/F (3ch) Variable Speed Control playback eSD/eMMC, UHSI, w/o CPRM (0.5 to 4.0 times speed) SD0: eSD/eMMC boot supported (Internal ROM While WMA and AAC playback, up to 2.0 time Boot function) 1.8 V dedicated power supply speed SD1: Multiplexed w/ Memory Stick I/F While PCM playback, up to 4.0 times speed 1.8 V dedicated power supply While MP3 playback w/ hard wired decoder, SD2: 1.8 V dedicated power supply up to 4.0 times speed Memory Stick I/F (1ch) Noise Canceller, etc. Multiplexed w/ SD1 JTAG ICE USB2.0 Host (HS/FS/LS) Controller, Device (HS/FS) Controller. Integrated PHY Xtal (XT1) is required for USB function. 48 MHz for Host, and 12,20,24,48 MHz for device w/o OTG function. Host and Device share an integrated PHY. 1 MPEG Layer3 audio coding technology licensed from Fraunhofer IIS and Thomson. Supply of this product does not convey license nor imply any right to distribute content created with this product in revenuegenerating broadcast systems (terrestrial, satellite, cable and/or other distribution channels), streaming applications (via Internet, intranets and/or networks), other content distribution systems (payaudio or audioondemand applications and the like) or on physical media (compact discs, digital versatile discs, semiconductor chips, hard drives, memory cards and the like). For details, please visit