MC100EP105MNG ON Semiconductor

MC10EP105, MC100EP105 3.3V / 5VECL Quad 2Input Differential AND/NAND Description The MC10/100EP105 is a quad 2input differential AND/NAND gate. Each gate is functionally equivalent to the EP05 and LVEL05 MC10EP105, MC100EP105 D0b D1a D1a D1b D1b D2a D2a D2b D0b D1a D1a D1b D1b D2a D2a D2b 24 23 22 21 20 19 18 17 24 23 22 21 20 19 18 17 25 16 25 16 D2b D0b D2b D0b 15 26 D0a D3a 26 15 D0a D3a 27 14 D0a D3a 27 14 D0a D3a 28 13 MC10EP105 V V 28 13 V V EE CC EE CC Exposed Pad (EP) MC100EP105 12 29 Q0 D3b 29 12 Q0 D3b 30 11 Q0 D3b 30 11 Q0 D3b 31 10 V V CC EE 31 10 V V CC EE 32 9 V NC CC 32 9 V NC CC 12345678 12 3 4 5 6 7 8 V Q1 Q1 Q2 Q2 Q3 Q3 V CC CC V Q1 Q1 Q2 Q2 Q3 Q3 V CC CC Warning: All V and V pins must be externally connected CC EE to Power Supply to guarantee proper operation. Figure 1. 32Lead LQFP Pinout (Top View) Figure 2. 32Lead QFN Pinout (Top View) Table 1. PIN DESCRIPTION D0a Q0 D0a PIN FUNCTION D0b Dna*, Dnb*, Dna*, Dnb* ECL Data Inputs Q0 D0b Qn, Qn ECL Data Outputs V Positive Supply CC D1a Q1 V Negative Supply EE D1a D1b NC No Connect Q1 D1b * Pins will default LOW when left open. D2a Q2 D2a Table 2. TRUTH TABLE D2b Q2 D2b Dna Dnb Dna Dnb Qn Qn LL H H L H D3a Q3 L HHL L H D3a H L LH LH D3b HH L L H L Q3 D3b V EE Figure 3. Logic Diagram