3.3 V/5 VECL Quad D Flip-Flop with Set, Reset, and Differential Clock MC10EP131, MC100EP131 Description www.onsemi.com The MC10/100EP131 is a Quad Masterslaved D flipflop with common set and separate resets. The device is an expansion of the E131 with differential common clock and individual clock enables. With AC performance faster than the E131 device, the EP131 is ideal for applications requiring the fastest AC performance available. LQFP32 Each flipflop may be clocked separately by holding Common FA SUFFIX CASE 561AB Clock (C ) LOW and C HIGH, then using the differential Clock C C Enable inputs for clocking (C , C ). 0 3 0 3 Common clocking is achieved by holding the differential inputs MARKING DIAGRAM* C LOW and C HIGH while using the differential Common 0 3 0 3 Clock (C ) to clock all four flipflops. When left floating open, any C differential input will disable operation due to input pulldown resistors MCxxx forcing an output default state. EP131 AWLYYWWG Individual asynchronous resets (R ) and an asynchronous set 0 3 (SET) are provided. Data enters the master when both C and C are LOW, and C 0 3 transfers to the slave when either C or C (or both) go HIGH. xxx = 10 or 100 C 0 3 A = Assembly Location The 100 Series contains temperature compensation. WL = Wafer Lot YY = Year Features WW = Work Week 460 ps Typical Propagation Delay G = PbFree Package Maximum Frequency > 3 GHz Typical (Note: Microdot may be in either location) Differential Individual and Common Clocks *For additional marking information, refer to Application Note AND8002/D. Individual Asynchronous Resets Asynchronous Set ORDERING INFORMATION PECL Mode Operating Range: V = 3.0 V to 5.5 V CC with V = 0 V EE Device Package Shipping NECL Mode Operating Range: V = 0 V MC10EP131FAG 250 Units / Tray CC LQFP32 with V = 3.0 V to 5.5 V (PbFree) EE Open Input Default State 250 Units / Tray MC100EP131FAG LQFP32 (PbFree) Safety Clamp on Inputs LQFP32 2000 / Tape & MC100EP131FAR2G Q Output Will Default LOW with Inputs Open or at V EE (PbFree) Reel PbFree Packages are Available For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2006 1 Publication Order Number: April, 2021 Rev. 11 MC10EP131/DMC10EP131, MC100EP131 Q Q Q Q Q Q Q Q 3 3 2 2 1 1 0 0 24 23 22 21 20 19 18 17 25 16 S V V CC CC Q D D Q 3 3 26 15 C R 3 0 C 3 27 14 Q C D C Q 3 3 0 3 R 28 13 V V EE CC R 3 32Lead LQFP Pinout 29 12 D (Top View) C 3 0 S D 30 11 Q 2 Q R C D 2 3 0 C 2 31 10 SET R 1 C Q Q 2 2 32 9 R D V 2 EE 12345678 R 2 SET R C C C C C C D 2 2 2 C C 1 1 1 C C Warning: All V and V pins must be externally connected CC EE C C to Power Supply to guarantee proper operation. Figure 1. 32Lead LQFP Pinout (Top View) R 1 R C 1 Q Q 1 Table 1. PIN DESCRIPTION C 1 PIN FUNCTION D Q 1 1 Q D * ECL Data Inputs 0 3 D S C *, C * ECL Separate Clock Inputs 0 3 0 3 C *, C * ECL Common Clock Inputs C C R 0 R * ECL Asynchronous Reset 0 3 R C 0 Q Q 0 SET* ECL Asynchronous Set C 0 Q , Q ECL Data Outputs 0 3 0 3 D Q Q 0 0 D S V Positive Supply CC V Negative Supply EE V EE * Pins will default LOW when left open. Figure 2. Logic Diagram Table 2. TRUTH TABLE D S* R* CLK Q L L L Z L H L L Z H X H L X H X L H X L X H H X Undef Z = LOW to HIGH Transition * Pins will default low when left open. www.onsemi.com 2