MC10E131, MC100E131 5 VECL 4Bit D FlipFlop Description The MC10E/100E131 is a quad master-slave D-type flip-flop with differential outputs. Each flip-flop may be clocked separately by holding Common Clock (C ) LOW and using the Clock Enable (CE) C www.onsemi.com inputs for clocking. Common clocking is achieved by holding the CE inputs LOW and using C to clock all four flip-flops. In this case, the C CE inputs perform the function of controlling the common clock, to each flip-flop. Individual asynchronous resets are provided (R). Asynchronous set controls (S) are ganged together in pairs, with the pairing chosen to reflect physical chip symmetry. PLCC28 Data enters the master when both C and CE are LOW, and transfers C FN SUFFIX to the slave when either C or CE (or both) go HIGH. CASE 77602 C The 100 Series contains temperature compensation. Features MARKING DIAGRAM* 1100 MHz Min. Toggle Frequency Differential Outputs 1 Individual and Common Clocks Individual Resets (asynchronous) MCxxxE131G Paired Sets (asynchronous) AWLYYWW PECL Mode Operating Range: V = 4.2 V to 5.7 V with V = 0 V CC EE NECL Mode Operating Range: V = 0 V with V = 4.2 V to 5.7 V CC EE xxx = 10 or 100 Metastability Time Constant is 200 ps. A = Assembly Location WL = Wafer Lot Internal Input 50 k Pulldown Resistors YY = Year ESD Protection: WW = Work Week G = Pb-Free Package Human Body Model > 2 kV Machine Model > 200 V *For additional marking information, refer to Application Note AND8002/D. Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Moisture Sensitivity Level: 3 (Pb-Free) For Additional Information, see Application Note AND8003/D ORDERING INFORMATION Flammability Rating:UL 94 V0 0.125 in, Oxygen Index: 28 to 34 Transistor Count = 240 devices Device Package Shipping These Devices are Pb-Free, Halogen Free and are RoHS Compliant MC10E131FNG PLCC28 37 Units/Tube (Pb-Free) MC10E131FNR2G PLCC28 500/Tape & Reel (Pb-Free) MC100E131FNG PLCC28 37 Units/Tube (Pb-Free) MC100E131FNR2G PLCC28 500/Tape & Reel (Pb-Free) For information on tape and reel specifications, in- cluding part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: July, 2016 Rev. 12 MC10E131/DMC10E131, MC100E131 S Q D D Q 3 3 CE 3 Q Q 3 R R D CE R V Q Q 3 2 2 2 CCO 3 3 R 3 25 24 23 22 21 20 19 S D Q D Q Q 2 CE 18 2 3 26 2 CE 2 Q D 17 27 2 Q Q 3 2 R R 2 S 28 16 V 12 CC S 03 Pinout: 28-Lead PLCC S 12 1 V 15 Q EE 1 (Top View) C C R 1 C 2 14 Q C 1 R Q Q 1 CE 1 S 3 13 Q 03 0 D D Q 1 Q 1 D 4 Q S 0 12 0 56 7 8 9 10 11 R 0 CE R CE R D R NC V 1 0 0 1 1 CCO Q Q 0 CE 0 * All V and V pins are tied together on the die. CC CCO D D Q Q 0 0 S Warning: All V , V , and V pins must be externally CC CCO EE connected to Power Supply to guarantee proper operation. Figure 1. Pinout Diagram Figure 2. Logic Diagram Table 1. PIN DESCRIPTION PIN FUNCTION D D ECL Data Inputs 0 3 CE CE ECL Clock Enables (Individual) 0 3 R R ECL Resets 0 3 C ECL Common Clock C S , S ECL Sets (paired) 03 12 Q Q , Q Q ECL Differential Outputs 0 3 0 3 V , V Positive Supply CC CCO V Negative Supply EE NC No Connect www.onsemi.com 2