MC10E141 5 V ECL 8Bit Shift Register Description The MC10E/100E141 is an 8-bit full-function shift register. The E141 performs serial/parallel in and serial/parallel out, shifting in either direction. The eight inputs D D accept parallel input data, 0 7 www.onsemi.com while DL/DR accept serial input data for left/right shifting. The Qn outputs do not need to be terminated for the shift operation to function. To minimize noise and power, any Q output not used should be left unterminated. The select pins, SEL0 and SEL1, select one of four modes of operation: Load, Hold, Shift Left, Shift Right, according to the Function Table. Input data is accepted a set-up time before the positive clock edge. A PLCC28 HIGH on the Master Reset (MR) pin asynchronously resets all the FN SUFFIX registers to zero. CASE 77602 The 100 Series contains temperature compensation. Features 700 MHz Min. Shift Frequency MARKING DIAGRAM* 8-Bit 1 Full-Function, Bi-Directional Asynchronous Master Reset Pin-Compatible with E241 MCxxxE141FNG PECL Mode Operating Range: V = 4.2 V to 5.7 V CC AWLYYWW with V = 0 V EE NECL Mode Operating Range: V = 0 V CC with V = 4.2 V to 5.7 V EE xxx = 10 Internal Input 50 k Pulldown Resistors A = Assembly Location ESD Protection: WL = Wafer Lot YY = Year > 2 kV Human Body Model WW = Work Week > 200 V Machine Model G = Pb-Free Package Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test *For additional marking information, refer to Moisture Sensitivity: Level 3 (Pb-Free) Application Note AND8002/D. (For Additional Information, see Application Note AND8003/D) Flammability Rating: UL 94 V0 0.125 in, Oxygen Index: 28 to 34 ORDERING INFORMATION Transistor Count = 565 Devices Device Package Shipping These Devices are Pb-Free, Halogen Free and are RoHS Compliant MC10E141FNG PLCC28 37 Units / Tube (Pb-Free) MC10E141FNR2G PLCC28 500 Tape & Reel (Pb-Free) For information on tape and reel specifications, in- cluding part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: July, 2016 Rev. 8 MC10E141/DMC10E141 Table 1. PIN DESCRIPTION SEL0 DL D D D V Q 7 6 5 CCO 7 PIN FUNCTION 25 24 23 22 21 20 19 SEL1 Q 26 18 6 D D ECL Parallel Data Inputs 0 7 DL, DR ECL Serial Data Inputs CLK Q 27 17 5 SEL0, SEL1 ECL Mode Select In Inputs CLK ECL Clock MR 28 16 V CC Q -Q ECL Data Outputs 0 7 MR ECL Master Reset 1 Pinout: 28-Lead V 15 NC EE V , V Positive Supply* CC CCO PLCC (Top View) V Negative Supply EE DR 2 NC No Connect 14 V CCO *From V pin to each V pin is an internal 100 CC CCO D 3 13 Q 0 4 resistor. D 4 1 Q 12 3 Table 2. FUNCTION TABLE 567 8 9 10 11 SEL0 SEL1 FUNCTION D D D V Q Q Q 2 3 4 CCO 0 1 2 L Load LL * All V and V pins are tied together on the die. CC CCO H Shift Right (D to D ) LL n n + 1 L Shift Left (D to D ) Warning: All V , V , and V pins must be externally HH n n 1 CC CCO EE H Hold connected to Power Supply to guarantee proper operation. HH Figure 1. 28-Lead Pinout DL BITS 1 6 Q D Q Q D D DR R R R D D 7 Q Q Q 0 7 D 0 SEL1 SEL0 CLK MR Figure 2. Logic Diagram Table 3. EXPANDED FUNCTION TABLE Function DL DR SEL0 SEL1 MR CLK Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Load X X L L L Z D0 D1 D2 D3 D4 D5 D6 D7 Shift Right X L L H L Z L Q0 Q1 Q2 Q3 Q4 Q5 Q6 X H L H L Z H L Q0 Q1 Q2 Q3 Q4 Q5 Shift Left L X H L L Z L Q0 Q1 Q2 Q3 Q4 Q5 L H X H L L Z Q0 Q1 Q2 Q3 Q4 Q5 L H Hold X X H H L Z Q0 Q1 Q2 Q3 Q4 Q5 L H X X H H L Z Q0 Q1 Q2 Q3 Q4 Q5 L H Reset X X X X H X L L L L L L L L www.onsemi.com 2